Patents Assigned to Elonex Technologies
  • Patent number: 5565897
    Abstract: A system for adjusting signals to a CRT in a video monitor utilizes an interactive display having shapes that appear rectangular on a properly adjusted monitor and dragging handles associated with the shapes. Control routines executed on a host computer associate pointer position and movement in dragging the handles with creation of signals to be sent to the monitor to correct signals to the CRT to produce a properly sized, positioned, and shaped display. In one embodiment, digital values are placed in serial packets on a VSYNC line from the host to the video monitor, and a microcontroller in the monitor receives the digital values and drives circuitry in the monitor according to the received commands and data to adjust the signals to the CRT to correct the display.
    Type: Grant
    Filed: September 16, 1994
    Date of Patent: October 15, 1996
    Assignee: Elonex Technologies, Inc.
    Inventors: Dan Kikinis, Pascal Dornier
  • Patent number: 5561772
    Abstract: A compressed I/O bus system for a general-purpose computer multiplexes 32 bit data and addresses on 32 of 42 dedicated parallel signal paths, and optimizes the bus structure by mapping bus requests made by peripheral devices to "high" memory portions of system RAM not dedicated to other purposes. In one aspect a bus controller is programmable to select translation routines stored in system RAM, allowing various models and types of CPUs to be supported. In this aspect, supported CPUs are interchangeable in the system. In another aspect a default interface attaches to the compressed I/O bus of the invention, and translates bus states between the optimized compressed bus and one of an ISA bus or an EISA bus.
    Type: Grant
    Filed: July 26, 1994
    Date of Patent: October 1, 1996
    Assignee: Elonex Technologies, Inc.
    Inventors: Pascal Dornier, Dan Kikinis, William J. Seiler, William S. Jacobs
  • Patent number: 5542035
    Abstract: A system for managing power levels for a general purpose computer having a standby and a full-power mode of operation provides apparatus and a method for monitoring times of user input and control routines for using the times of user input to calculate optimum times for initiating full power operation and standby mode. The control routines are configured to provide the optimum times to a real time clock that remains powered in the standby mode, which triggers switching elements to initiate full power and standby mode. In one embodiment of the system, startup and standby may be initiated either by user input or automatically by the power management system. Startup and standby initiation times may be different for different days and time periods based on both preprogrammed and calculated values.
    Type: Grant
    Filed: October 27, 1993
    Date of Patent: July 30, 1996
    Assignee: Elonex Technologies
    Inventors: Dan Kikinis, Pascal Dornier
  • Patent number: 5539878
    Abstract: A method for testing CPU microprocessors having internal cache involves testing one IU and a portion of the internal cache, then loading a cache test routine to the tested portion of internal cache and causing that routine to be executed by the tested IU to test the previously untested portion of the internal cache while simultaneously testing any other IUs and circuitry on the CPU microprocessor. A system is disclosed for performing the method.
    Type: Grant
    Filed: June 16, 1995
    Date of Patent: July 23, 1996
    Assignee: Elonex Technologies, Inc.
    Inventor: Dan Kikinis
  • Patent number: 5539621
    Abstract: An interconnection topography for microprocessor-based communication nodes consists of opposite arrays of client nodes and resource nodes, with each client node connected to one resource node by a data transfer link, each resource node connected to a resource trunk by a data transfer link, and each node connected to just four neighboring nodes by data transfer links. Communication nodes in the topography are microprocessor controlled, and comprise random access memory and data routing circuitry interfaced to the data transfer links. In one aspect resource nodes are provided with a map of the interconnection topography for use in routing data. In another aspect, individual ones of the communication nodes are programmed as servers for receiving client requests and scheduling routing of resource data.
    Type: Grant
    Filed: June 23, 1995
    Date of Patent: July 23, 1996
    Assignee: Elonex Technologies, Inc.
    Inventor: Dan Kikinis
  • Patent number: 5539616
    Abstract: A modular computer has a framework with module bays for receiving CPU modules, power modules, and peripheral function modules such as floppy and hard disk drives. The framework has a built-in compressed bus and a variety of function modules which can be plugged into any one of the module bays. Function modules include, but are not limited to, CPU, power, floppy disk, hard disk, RAM memory, LAN communication, modem, FAX communication, and data acquisition. In some embodiments function modules are provided for communicating with separate input means, such as voice, keyboards, and pen-pads. In one aspect the module bays and the function modules are configured according to dimensional and connective standards of the Personal Computer Memory Card International Association.
    Type: Grant
    Filed: November 29, 1993
    Date of Patent: July 23, 1996
    Assignee: Elonex Technologies, Inc.
    Inventor: Dan Kikinis
  • Patent number: 5537343
    Abstract: A personal digital assistant module with a local CPU, memory, and I/O interface has a host interface comprising a bus connected to the local CPU and a connector at a surface of the personal digital assistant for interfacing to a bus connector of a host general-purpose computer, providing direct bus communication between the personal digital assistant and the host general-purpose computer. In an embodiment, the personal digital assistant also has a means for storing a security code.The personal digital assistant according to the invention forms a host/satellite combination with a host computer having a docking bay, wherein upon docking a docking protocol controls access by the host to memory of the personal digital assistant based on one or more passwords provided by a user to the host. In another embodiment the personal digital assistant also has an expansion port connected to the local CPU, and expansion peripheral devices may be connected and operated through the expansion port.
    Type: Grant
    Filed: December 28, 1994
    Date of Patent: July 16, 1996
    Assignee: Elonex Technologies, Inc.
    Inventors: Dan Kikinis, Pascal Dornier, William J. Seiler
  • Patent number: 5528480
    Abstract: A power supply for producing a regulated dc output from an ac primary input incorporates a convention rectifying and filtering circuitry feeding a switching circuit for providing a high frequency, substantially rectangular voltage waveform to a high frequency transformer. The output of the transformer is provided to a synchronous buck converter having a grounded line and an ungrounded line, with a first FET switch in the ungrounded line and a second FET switch connected from the output of the first FET switch to the grounded line. A controller in the synchronous buck converter switches the FETs according to the input voltage waveform to achieve rectification. In another aspect, two FETs are placed in opposite polarity in the ungrounded line and switched together, and the controller also alters the duty cycle of the switching in accordance with the magnitude of a regulated output produced from the output of the synchronous buck converter, to achieve precise regulation.
    Type: Grant
    Filed: April 28, 1994
    Date of Patent: June 18, 1996
    Assignee: Elonex Technologies, Inc.
    Inventors: Dan Kikinis, Thomas Lo
  • Patent number: 5473506
    Abstract: A modular computer with docking bays for receiving functional modules and connecting the functional modules to internal computer circuitry has translatable heat-sink structures for contacting docked functional modules to extract waste heat generated by operation of the functional modules. The structures are mechanically actuated to retract to provide clearance for insertion and withdrawal of functional modules, and to advance to contact modules when docked. Heat-sink structures are shaped in some embodiments to securely retain docked modules, and in some instances, the translation of the heat-sink structures is by electrically operable actuators, which may be actuated by signals from a CPU of the modular computer. In these instances, the computer may be configured to require a security code or special input sequence to retract the heat-sink structures allowing a module to be removed.
    Type: Grant
    Filed: November 12, 1993
    Date of Patent: December 5, 1995
    Assignee: Elonex Technologies, Inc.
    Inventor: Dan Kikinis
  • Patent number: 5457785
    Abstract: A bus interface system for expanding the I/O capability of a portable computer utilizes a parallel port connector with master interface circuitry connected to the internal ISA I/O bus of the portable computer and driving a 25-conductor Centronics-type cable as an intermediate bus. The master interface circuitry is device-driver-transparent, and multiplexes address, data, and control information over a byte-wide avenue of the intermediate bus according to premapped state translation tables. In a preferred embodiment a single peripheral I/O device comprising a slave circuitry may be connected to the 25-pin port, and the slave circuitry demultiplexes the intermediate bus states, providing a synthesized sub-set of ISA states to drive the peripheral device. In another embodiment a docking box comprises a bus with multiple I/O ports, such as a network port, a COM serial port, and additional floppy and hard disk drives.
    Type: Grant
    Filed: February 10, 1993
    Date of Patent: October 10, 1995
    Assignee: Elonex Technologies, Inc.
    Inventors: Dan Kikinis, William J. Seiler, Pascal Dornier, William S. Jocobs