Patents Assigned to Elpida Memory
  • Patent number: 8377745
    Abstract: A method of forming a semiconductor device includes filling a gap of a semiconductor chip stack while carrying out a first heating process which heats the semiconductor chip stack from upper and lower portions of the semiconductor chip stack.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: February 19, 2013
    Assignee: Elpida Memory
    Inventors: Noriou Shimada, Tomoyuki Fujishima
  • Patent number: 7694245
    Abstract: A method for designing a semiconductor package is disclosed, wherein the semiconductor package comprises a semiconductor chip and an adjustment target. A first target variable is calculated in consideration of a first transition state where an output level of the semiconductor chip changes from a low level to a high level. A second target variable is calculated in consideration of a second transition state where an output level of the semiconductor chip changes from the high level to the low level. Inferior one of the first and the second target variables is selected as a main target variable. The main target variable and a predetermined constraint represented in frequency domain are compared to decide design guidelines for the adjustment target.
    Type: Grant
    Filed: February 27, 2007
    Date of Patent: April 6, 2010
    Assignee: Elpida Memory
    Inventors: Mitsuaki Katagiri, Satoshi Nakamura, Takashi Suga, Yoji Nishio, Satoshi Isa, Satoshi Itaya
  • Publication number: 20080210999
    Abstract: A semiconductor device includes: a semiconductor substrate; a memory cell selection transistor that is formed on the semiconductor substrate and has a source and a drain; a contact plug; a polysilicon interlayer film that is formed above the memory cell selection transistor and has a cylinder-shaped through-hole; and a storage capacity part that is formed in the through-hole and is connected to the source and the drain of the memory cell selection transistor via the contact plug, wherein a boundary between a bottom and a side wall of the through-hole has a curved surface.
    Type: Application
    Filed: January 28, 2008
    Publication date: September 4, 2008
    Applicant: ELPIDA MEMORY
    Inventor: Mitsuhiro HORIKAWA
  • Publication number: 20080068918
    Abstract: A semiconductor memory device includes plural banks, defect relief circuits individually provided for these banks, a defective-address storing circuit that stores defective addresses, and a comparing circuit that compares an access-requested address with a defective address. The defective-address storing circuit and the comparing circuit are allocated in common to two banks, respectively. With this arrangement, a chip area can be decreased.
    Type: Application
    Filed: September 12, 2007
    Publication date: March 20, 2008
    Applicant: Elpida Memory
    Inventor: Naoshisa Nishioka