Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high-k phase of a subsequently deposited dielectric layer. The high-k dielectric layer includes a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.

Abstract: A method of making a semiconductor apparatus provides a plurality of electrode pads on a main surface of a semiconductor chip, and a plurality of bump electrodes on the electrode pads. The method also provides a wired board which is allocated in a side of the main surface of the chip and is positioned in a central area of the main surface of the chip so as to be separated from an edge part of the chip by at least 50 ?m or more, a plurality of external terminals on the wired board and which are electrically connected to a plurality of bump electrodes through wirings of the wired board, and a sealing part between the chip and the wired board, the sealing part being made of underfill material that covers a connection part between the bump electrode and the wiring.

Abstract: High-speed operation is achieved without increase in a circuit current and unstable operation of data strobe signal level due to collision between data strobe signals. Each of RAMs 11a and 11b outputs a data signal DQ and a data strobe signal DQS indicative of an output timing of the data signal. RAM 11a includes a strobe signal control unit 15a that determines whether RAM 11b connected in parallel with the RAM 11a is in a read state or not, and delays an output start timing of data strobe signal DQS when the RAM 11b is in the read state. Strobe signal control unit 15a of the RAM 11a controls output start timing so that a latter half portion of a preamble period of the data strobe signal DQS to be output coincides with a postamble period of the data strobe signal DQS output by the RAM 11b.