Patents Assigned to EM Microelectronics-Marin SA
  • Patent number: 6492861
    Abstract: The charge pump device includes, in a cascade arrangement, a plurality of stages (1 to N) for transferring a potential charge from one stage to the next in response to clock signals (PHI, PA, PHINOT, PB), each stage including, arranged between an input (Ai) and an output (Ai+1), a switching circuit (100, 200) and a storage capacitor (Ca; Cb). Each switching circuit is formed of a first transistor (110; 130) and a second transistor (120; 140), the drains of the first and second transistors being connected to the input (Ai) of the stage, the source of the first transistor (110; 130) being connected to the gate of the second transistor (120; 140) and the source of the second transistor being connected to output (Ai+1) of the stage and to the gate of the first transistor. At each of the stages (1 to N) there are provided starting-up means (300; 400; 500) for keeping said second transistor (120, 140) in a non conducting state between two activation cycles of said charge pump device.
    Type: Grant
    Filed: February 5, 2001
    Date of Patent: December 10, 2002
    Assignee: EM Microelectronic-Marin SA
    Inventors: Olivier Rey, Christian Bonjour
  • Patent number: 6470045
    Abstract: The communication protocol between at least one transceiver unit (communication unit) and transponders or transceivers (transponders) associated with said unit is characterised in that at least one initial command is sent by said unit to generate interaction with said transponders entering its field of action, said initial command having at least partially a coding with a specific time structure which is different from the basic time structure used for encoding said coded data. The specific time structure has greater coding time periods than the coding time periods of the basic time structure. At least one coding period of the specific time structure has a constant characteristic electric value over a time interval greater than the duration of said constant characteristic electric value able to appear in any bit sequence having the basic time structure.
    Type: Grant
    Filed: September 10, 1998
    Date of Patent: October 22, 2002
    Assignee: Em Microelectronic-Marin SA
    Inventor: Vincent Fuentes
  • Patent number: 6462647
    Abstract: The present invention concerns an active transponder (30) including an antenna (32) for exchanging a radioelectric signal (34), processing means (36), an accumulator (38) able to supply a first power supply signal (V1), and storage means (40) able to store the power originating from the received radioelectric signal, and to supply a second power supply signal (V2). This transponder further includes: two means (42, 46) for comparing the two power supply signals to a minimum threshold (Vmin) and, in response, providing two control signals (V3, V4); and charging means (50) controlled by the two control signals, so that the accumulator can be charged, via the charging means, from the stored power. One advantage of such a transponder is that the accumulator can be automatically recharged, as soon as the latter is no longer sufficiently charged to assure the functions of the transponder.
    Type: Grant
    Filed: October 29, 1999
    Date of Patent: October 8, 2002
    Assignee: EM Microelectronic-Marin SA
    Inventor: Thierry Roz
  • Publication number: 20020142508
    Abstract: The present invention concerns the field of microstructures and in particular microstructures made via CMOS technology on semiconductor substrates intended to undergo micro-machining by wet chemical etching, in particular by a KOH etchant.
    Type: Application
    Filed: February 8, 2002
    Publication date: October 3, 2002
    Applicant: EM Microelectronic-Marin SA
    Inventor: Ulrich Munch
  • Patent number: 6459326
    Abstract: A method and a device for generating a substantially temperature independent current (I1) are described. To generate this current (I1), a conventional current generator circuit including an operational amplifier (11) controlling a transistor (12) having one (12a) of its current electrodes (12a, 12b) connected to a resistor (13) and to an input terminal (11b) of the operational amplifier (11), is used. According to the invention, a temperature stable input voltage (Vin) is applied at the other input terminal (11a) of the operational amplifier (11), and the latter is arranged so that it has an offset voltage (Vos(T)) between its input terminals (11a, 11b) having a temperature dependence, this offset voltage (Vos(T)) and the input voltage (Vin) being adjusted to compensate for the temperature dependence of the resistor (13) such that the current generated (I1) is substantially temperature independent.
    Type: Grant
    Filed: June 7, 2001
    Date of Patent: October 1, 2002
    Assignee: EM Microelectronic-Marin SA
    Inventor: Arthur Descombes
  • Patent number: 6409071
    Abstract: Method for welding two end portions (6, 8) of a coil (not shown) onto two electric contact pads or bumps (24, 26) of an integrated circuit (2) or an electronic unit of small dimensions. This welding method is characterised in that, prior to the actual welding step, a preliminary step is provided consisting in removing at least partially the insulating sheath from the electric wire (10) at least at the locations of the two end portions (6, 8) provided for the welding onto said electric contact pads or bumps (24, 26). The insulating sheath is removed locally by means of heat application, in particular using a heating press (58) working at a sufficiently high temperature to melt or sublimate the insulating sheath. The welding step is achieved at a much lower temperature than the temperature of the preliminary step, which allows the heat and mechanical stress to be reduced for the integrated circuit (2) and the bumps (24, 26) during welding of the ends (6, 8) onto said bumps.
    Type: Grant
    Filed: March 27, 2000
    Date of Patent: June 25, 2002
    Assignee: EM Microelectronic Marin SA
    Inventors: Elko Doering, Pascal Cattin, Uwe Thiemann
  • Patent number: 6377429
    Abstract: The invention concerns a protective circuit (10) for protecting a rechargeable battery (1) against currents of too high intensity. The protective circuit (10) includes detection and comparison means (30, 31, 32) for generating a control signal (OVRC) in response to the comparison of a reference voltage (VREF) and a measuring voltage (VM) representative of the charge or discharge current (ICH, IDCH) passing through the battery (1). According to the invention, the detection and comparison means (30, 31, 32) include adjustment means (32) for compensating a temperature dependence of the measuring voltage (VM) and/or the reference voltage (VREF), these adjustment means (32) including means for generating diode voltages (VBE1 to VBE5).
    Type: Grant
    Filed: April 19, 2000
    Date of Patent: April 23, 2002
    Assignee: EM Microelectronic-Marin SA
    Inventor: Arthur Descombes
  • Patent number: 6337605
    Abstract: The present invention concerns an oscillator (20) intended to supply a periodic electric voltage (Vo) at a predetermined frequency (f). This oscillator includes: a reference source (23) able to provide a reference voltage (Vref), this reference source including a resistor (R) linked to said voltage; and supply means (24) able to receive the reference voltage and to supply said periodic voltage at said predetermined frequency, the supply means having a first temperature coefficient (&agr;24) so this frequency can vary under the influence of the temperature. This oscillator is characterised in that the resistor is formed to give the reference source a second temperature coefficient (&agr;23) equal to the first temperature coefficient, so that the temperature has the same influence on the reference voltage and on the supply means, which allows the periodic voltage to be supplied independently of the temperature.
    Type: Grant
    Filed: July 24, 2000
    Date of Patent: January 8, 2002
    Assignee: EM Microelectronic-Marin SA
    Inventor: Jean-Noël Divoux
  • Patent number: 6320399
    Abstract: The present invention concerns a method for measuring a chip integrated structure (1) including at least one coil (5) having a plurality of turns (6). The present invention is characterized on the following steps: measuring the resistance across the terminals of first and second portions of said coil (5), corresponding to two different numbers of turns of the coil; computing the ratio of the measured resistances across the terminals of first and second portions of the coil (5); comparing the ratio to a constant measured from a sample of resistance measurements made on coils of identical geometry; and determining the presence or the absence of a short circuit between at least two turns of one of said portions of said coil (5), when the ratio is different from or equal to said constant respectively. The present invention further concerns an integrated circuit which is able to allow implementation of the above mentioned measuring method.
    Type: Grant
    Filed: March 20, 1998
    Date of Patent: November 20, 2001
    Assignee: EM Microelectronic-Marin SA
    Inventors: Pascal Kunz, Antal Banyai
  • Patent number: 6314544
    Abstract: The object of the procedure according to the present invention is to characterise a voltage or current converter (20) intended to be connected to a capacitive circuit (32) arranged so as to provide a capacitance difference (C1−C2) to the converter. Said converter is arranged so as to be able to receive the capacitance difference provided by the circuit, and to provide an output voltage (Vo) which is a function of the capacitance difference and a bias signal. This procedure is characterised in that it includes a sequence of steps which consist in varying the bias signal, while keeping the capacitance difference constant and measuring in response the output voltage. One advantage of such a procedure lies in the fact that it allows the electric performance of the converter to be determined independently of the error link to the capacitance measuring.
    Type: Grant
    Filed: December 9, 1998
    Date of Patent: November 6, 2001
    Assignee: EM Microelectronic-Marin SA
    Inventors: Olivier Rey, Antal Banyai
  • Patent number: 6310827
    Abstract: The electronic memory (2) includes blocks (M1 to MN) associated respectively with protective sequences (P1 to PN) and decision units (D1 to DN) which control access to the memory blocks. The protective sequences include at least two bits. In order to protect the memory blocks against physical actions which could vary the inscribed code, access to a block is closed when the corresponding protective sequence has identical logical states.
    Type: Grant
    Filed: February 17, 2000
    Date of Patent: October 30, 2001
    Assignee: EM Microelectronic-Marin SA
    Inventor: Vincent Fuentes
  • Patent number: 6272320
    Abstract: A base station (13) for a contactless interrogation system includes an oscillating device (23) supplying a control signal having a frequency which is adjustable via adjusting circuits (21, 22), a circuits (24) for controlling an antenna connected to the base station (13) for transmitting information, decoding circuits (25, 26, 27) for decoding the information picked up by the antenna. The oscillating device (23) is a voltage controlled oscillator which is phase locked by the adjusting circuits (21, 22), so that the control signal frequency is determined by the base station (13) and is adapted to the antenna. The sensitivity of a contactless interrogation system comprising the base station (13) of the present invention is improved, its structure is simpler and its different components can be integrated in a same chip.
    Type: Grant
    Filed: January 12, 1998
    Date of Patent: August 7, 2001
    Assignee: EM Microelectronic-Marin SA
    Inventors: Navraj Nandra, Thierry Roz
  • Patent number: 6242325
    Abstract: The present invention concerns a method for optimising the etching rate of a polycrystalline layer having a predetermined composition comprising at least two chemical species arranged in the form of grains and grain boundaries, this layer having to be formed on a semiconductor substrate by a deposition process whose parameters have to be determined, and by a etching process with a reactive agent capable of reacting with the preponderant species in the layer. This method defines a structure parameter representing the grain boundary density of the layer, and comprises a step consisting in determining the smallest structure parameter value from among different samples having the predetermined composition, this value being considered as that which optimises the etching rate.
    Type: Grant
    Filed: February 9, 2000
    Date of Patent: June 5, 2001
    Assignee: EM Microelectronic-Marin SA
    Inventors: Edgar Schönbächler, Baudouin Lecohier
  • Patent number: 6239967
    Abstract: The electronic assembly (20) includes an electronic unit (24), formed of an electronic module (26) and two conductive tongues (28, 30) defining two electric contact pads of said electronic unit, and a coil (22). The body (40) of the coil (22) is partially superposed onto the two tongues and fixed to the latter in a durable manner by means of a solidified binder material. The two ends of the coil are bonded respectively onto the two tongues (28, 30).
    Type: Grant
    Filed: October 8, 1998
    Date of Patent: May 29, 2001
    Assignee: EM Microelectronic-Marin SA
    Inventor: Alain Juan
  • Patent number: 6225851
    Abstract: The invention concerns a temperature level detection circuit including means (B1, B2, B3, 11, 12, 21, 31, 32) for generating diode voltages (VBE1 to VBE5) and calculating means including capacitive elements (51, 52, 53) and switching means (SW1 to SW4) arranged to connect selectively and sequentially, during first and second phases, the capacitive elements (51, 52, 53) to the means generating said diode voltages (VBE1 to VBE5). During the second phase, the calculating means generating a temperature signal representative of the temperature level being greater than or less than a determined temperature threshold (Tlimit) defined as the temperature value for which the equation &agr;1(VBE2−VBE1)+&agr;2(VBE3+&agr;3 (VBE5−VBE4)) becomes zero, where &agr;1, &agr;2, and &agr;3 are first, second and third proportionality coefficients determined by the values of the capacitive elements.
    Type: Grant
    Filed: April 19, 2000
    Date of Patent: May 1, 2001
    Assignee: EM Microelectronic-Marin SA
    Inventor: Arthur Descombes
  • Patent number: 6191840
    Abstract: The invention concerns a manufacturing method for electro-optical or electrochemical photovoltaic cells (10), each cell (10) including front (1) and back (2) substrates bonded to each other by a sealing frame in which an active medium is confined, each frame (12) having, for this purpose, a filling aperture (14), the cell (10) further including contact pads (8) for establishing the electric connection between the electrodes (4, 6) of said cell (10) and an electric supply or control circuit, a method wherein the cells (10) are separated individually by means of a water jet and the rectilinear edges (24) scribed on one of the substrates (1, 2) in order to allow the contact pads (8) of the cells (10) to appear are situated in a location not opposite the filling aperture (14) thereof.
    Type: Grant
    Filed: March 18, 1999
    Date of Patent: February 20, 2001
    Assignee: EM Microelectronic-Marin SA
    Inventor: Patrick Bon
  • Patent number: 6184664
    Abstract: A voltage regulator circuit (1) able to detect a latch-up phenomenon disturbing the voltage to be regulated, to suppress such phenomenon and re-establish the voltage at a predetermined level. The circuit a bipolar transistor (2), a resistor (5) and substantially constant voltage supply means (6). The circuit (1) also includes voltage detection means (11) arranged to receive the regulated voltage (Vreg), and to supply a control voltage to said transistor (2) which can control the switching thereof between a conducting state and a blocked state, so that the transistor (2) is in the blocked state when latch-up causes the regulated voltage to drop below a first voltage level, and so that the transistor (2) is in the conducting state when the regulated voltage is lower than a second voltage level, the latch-up being suppressed below such level.
    Type: Grant
    Filed: November 4, 1999
    Date of Patent: February 6, 2001
    Assignee: EM Microelectronics-Marin SA
    Inventor: Antonio Martino Ponzetta
  • Patent number: 6150934
    Abstract: A communication system comprising a base station (20) and a plurality of transponders (TR; 21 to 26), the base station (20) emitting an electromagnetic field (1) defining a communication volume (2) in which several transponders (21, 22, 23) are susceptible to be situated. The transponders are adapted to generate identification messages (30) in response to the electromagnetic field (1). The base station (20) is adapted to selectively communicate with each transponder by generating communication initiation signals (40) in response to the identification messages (30). Each transponder is adapted to open a communication window (60) in response to a communication initiation signal (40) during which information may be exchanged and/or commands may be sent.
    Type: Grant
    Filed: January 22, 1999
    Date of Patent: November 21, 2000
    Assignee: EM Microelectronic-Marin SA
    Inventor: Maksimilijan Stiglic
  • Patent number: 6138936
    Abstract: A manufacturing method for electronic components (1) including a coil (10), in which a distributing device (34), carrying a pay-out reel (24) on which is wound a winding wire (6), places the wire (6) in contiguous regular turns (8) onto a core (2), this method being characterised in that a flux of ionised air is forced to flow onto the coil (10) during manufacturing to remove electrostatic charges produced during the winding of the coil.
    Type: Grant
    Filed: March 29, 1999
    Date of Patent: October 31, 2000
    Assignee: EM Microelectronic-Marin SA
    Inventors: Elko Doering, Pascal Cattin, Peter Jacob, Uwe Thiemann
  • Patent number: 6137273
    Abstract: The present invention concerns a circuit (30; 50) for supplying a first current (I3) to an external element (3), this current having to be supplied with high precision at a desired nominal value. The current supply circuit includes a first transistor (T3) through which the first current flows, an operational amplifier (A2) to a first input of which a reference voltage (Vref) is supplied, and to an output of which a control signal from the first transistor is supplied, and an external resistor (Re1; Re2). These the circuit is characterized in that it further includes a second transistor (T4) through which a second current (I4; I4/m) flows, said second current also flowing through the external resistor. Such an arrangement of the circuit according to the present invention allow the value of the first current to be trimmed with great precision to its nominal value.
    Type: Grant
    Filed: October 15, 1998
    Date of Patent: October 24, 2000
    Assignee: EM Microelectronic-Marin SA
    Inventors: Tim Bales, Serge Bitz