Patents Assigned to EM (US) Design, Inc
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Publication number: 20240211348Abstract: A method for managing data stored in a page (P) within a memory element of a memory system including a controller, the page (P) including at least one encoded data (E) consisting in a binary code being formed by a word (W 0-N) and its associated redundancy code (RC 0-N), the method including a step of storing a user data in this page (P) implemented by the controller, this step including a sub-step of performing error correction code (ECC) calculations on the user data providing an associated redundancy code (RC 0-N) corresponding to an erased redundancy code (RC E) for this user data if it has a reference binary code (br) of an erased word (W E) the erased redundancy code (RC E) having a binary value similar to that of the reference binary code (br).Type: ApplicationFiled: November 28, 2023Publication date: June 27, 2024Applicant: EM Microelectronic-Marin SAInventors: Stéphanie SALGADO, Thomas EBERHARDT
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Publication number: 20240211342Abstract: An electronic device including a Bluetooth communication unit configured to perform Bluetooth communication, this unit including a memory module containing a memory controller and a memory element equipped with at least one page (P) including at least one encoded data (E) including a binary code being formed by a word (W 0-N) and its associated redundancy code (RC 0-N), the memory controller being configured to store a user data in this page (P) by performing error correction code (ECC) calculations on this user data for providing an associated redundancy code (RC 0-N) corresponding to an erased redundancy code (RC E) for this user data, if this user data has a reference binary code of an erased word (W E), the erased redundancy code (RC E) having a binary value similar to that of the reference binary code.Type: ApplicationFiled: December 19, 2023Publication date: June 27, 2024Applicant: EM Microelectronic-Marin SAInventors: Stéphanie SALGADO, Thomas EBERHARDT
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Publication number: 20240210590Abstract: A skin contact sensing device (10) including a contact sensor (11) operable to generate electrical contact signals being indicative of a skin contact; a processor (12) connected to the contact sensor (11) and operable to process the electrical contact signals received from the contact sensor (11); and a memory (15) connected to the processor (12) and operable to store at least one calibration parameter, wherein the processor (12) is operable to ascertain a skin contact by processing of the electrical contact signals on the basis of the at least one calibration parameter and wherein the processor (12) is operable to read and to obtain the at least one calibration parameter from the memory (15).Type: ApplicationFiled: December 1, 2023Publication date: June 27, 2024Applicant: EM Microelectronic-Marin SAInventors: Sylvain QUELOZ, Gérald MONIN
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Publication number: 20240204758Abstract: A system with a low-drift on-chip (LD-RC) oscillator with lowered sensitivity to Random Telegraph Noise when generating a current (Id) for the LD-RC oscillator. A control resistor (R) is connected through an intermediary arrangement to one of a first MOS transistor (M1) or of a second MOS transistor (M2) between two terminals of a supply voltage source (Vdd). The gate of the first MOS transistor (M1) is connected to the gate of the second MOS transistor (M2), whereas the source of the first MOS transistor (M1) and the source of the second MOS transistor (M2) are connected to one terminal of the supply voltage source (Vdd), the control resistor (R) being connected to the other opposite terminal of the supply voltage source.Type: ApplicationFiled: November 7, 2023Publication date: June 20, 2024Applicant: EM Microelectronic-Marin SAInventors: Oskar KRENEK, Christoph KURATLI
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Publication number: 20240170298Abstract: A method to produce an integrated circuit including depositing a first layer of a metallic chemical constituent on a silicon substrate. A protective layer including a main chemical constituent different from the main chemical constituent of the first layer is then deposited on this first layer. An additional layer is deposited on the protective layer and includes a main chemical constituent different from, equivalent to or of equivalent size to the main chemical constituent of the first layer. A heat treatment operation is carried out at a first temperature to generate a silicide including the main constituent of the first layer and silicon according to a first stoichiometry. In a subsequent step, the additional layer and the protective layer are removed. In another step, a further heat treatment operation is carried out at a temperature greater than the first temperature in order to change the stoichiometry of the previously created silicide.Type: ApplicationFiled: October 27, 2023Publication date: May 23, 2024Applicant: EM Microelectronic-Marin SAInventors: Jean-Philippe JACQUEMIN, Jérôme LOLIVIER, René MEYER
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Patent number: 11990763Abstract: The present invention refers to a resonance generator system (10) capable of being used in signal capturing systems. The resonance generator system (10) comprises a signal input, a signal output, an oscillation capture module (11), a signal amplifier module (12), a phase alignment module (13), an oscillation transmitter module (14), at least one receiving antenna (15) and a power source (16). The present invention also refers to a method for capturing oscillatory signals by way of a resonance generator system (10).Type: GrantFiled: February 18, 2020Date of Patent: May 21, 2024Assignee: IBBX INOVAÇÃO EM SISTEMAS DE SOFTWARE E HARDWARE LTDAInventors: Luis Fernando Pigoso Destro, William Norberto Aloise, Vanderlei Goncalves
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Publication number: 20240145015Abstract: A method for reading data from a non-volatile memory array including a plurality of memory cells, each configured to store one bit of information. The method includes the steps of: powering on the memory array, where information from at least a first memory cell and a second memory cell is collectively associated with one bit of sensible data; b) reading a first memory cell value and a second memory cell value by comparing a reference value to a respective electrical property value of the respective memory cell to determine the respective memory cell value; c) adjusting the reference value in the event at least the first and second memory cell values have a first combination of logic state values to obtain an adjusted reference value; d) reading the first and second memory cell values by using the adjusted reference value to obtain a second combination of logic state values; and e) determining a sensible data bit value based on the obtained second combination of logic state values.Type: ApplicationFiled: July 27, 2023Publication date: May 2, 2024Applicant: EM Microelectronic-Marin SAInventors: Osama KHOURI, Yves GODAT
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Publication number: 20240126321Abstract: A clock distribution network (10) including a clock generator (14) configured to generate at least a processor clock signal and at least a first peripheral clock signal, the clock generator including a processor clock output (31), a first peripheral clock output (32) and a first clock request input (42). A first peripheral unit (22) via a first clock request input (42) is operable to trigger the clock generator (14) to transmit the first peripheral clock signal via the first peripheral clock output (32).Type: ApplicationFiled: September 26, 2023Publication date: April 18, 2024Applicant: EM Microelectronic-Marin SAInventor: Ovidiu SIMA
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Publication number: 20240127875Abstract: An address decoder unit (30) for a memory cell array (10), the address decoder unit (30) including an address decoder (31) including an address input (33) and a number of address outputs (34, 35, 36), the address decoder (31) being operable to select one of the address outputs (34, 35, 36) in response to receive a memory address at the address input (33); and an address selection circuitry (32) connected to the address decoder (31) and including a number of address selection outputs (44, 45, 46) each of which connectable the memory cell array and each of which corresponding to one memory address, wherein the address decoder unit (30) is switchable into a memory erase mode, in which the address selection circuitry (32) is operable to select all address selection outputs (44, 45, 46) of an address space above or beyond a memory address provided at the address input (33).Type: ApplicationFiled: September 26, 2023Publication date: April 18, 2024Applicant: EM Microelectronic-Marin SAInventors: Lubomir PLAVEC, Yves GODAT
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Patent number: 11962965Abstract: Disclosed is an earbud including a head housing configured for insertion into a user's auricle and having a sound emitting hole, and a stick housing extending downward from the head housing, wherein the stick housing is inclined inward.Type: GrantFiled: November 12, 2020Date of Patent: April 16, 2024Assignee: EM-TECH Co., Ltd.Inventors: Se Gwan Oh, Bae Nam Kim, Seung Kiu Jeong
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Publication number: 20240120911Abstract: A digital logic controller including a first delay cell connectable to a signal input and operable to generate a first time delayed input signal, a second delay cell connectable to the signal input and operable to generate a second time delayed input signal, a counter connectable to the signal input via the first delay cell, two logic units to generate reset signal by one of logic units and to generate set signal by the other of logic units, and connected between the set of delay cells and a flip-flop operable to generate a counter valid signal at a flip-flop output, a first comparator connected to an output of the counter and operable to compare a counter output signal with a first target, a first logic gate connected to the flip-flop output, connected to the first comparator and operable to temporally deactivate processing of the counter output signal.Type: ApplicationFiled: July 27, 2023Publication date: April 11, 2024Applicant: EM Microelectronic-Marin SAInventor: Ovidiu SIMA
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Patent number: 11949393Abstract: This application relates to an independent active electromagnetic interference filter module. In one aspect, the filter module includes a first element group including a noise sensing unit provided to sense electromagnetic noise, and a second element group including a compensating unit provided to generate a compensation signal for the electromagnetic noise. The first group and the second group may be respectively mounted on different substrates. According to some embodiments, the filter module can reduce a volume of each element constituting an electromagnetic interference filter module, implement a single modularization of a compact structure. The filter module can also improve electromagnetic interference noise reduction performance and a manufacturing method thereof.Type: GrantFiled: September 27, 2021Date of Patent: April 2, 2024Assignees: EM Coretech Co., Ltd., UNIST (Ulsan National Institute of Science and Technology)Inventors: Sang Yeong Jeong, Jin Gook Kim
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Publication number: 20240098924Abstract: A sealed electronic module (1) including at least one actionable part (2), the module (1) including a case (2) having: a watertight compartment (4) containing a printed circuit board (5), the compartment (4) being formed by a housing (13) with a unique opening (20), the housing (13) including the printed circuit board (5), and a sealing element (6a, 6b) configured for closing tightly the unique opening (20) by being fixed to the housing (13) and the printed circuit board (5).Type: ApplicationFiled: September 6, 2023Publication date: March 21, 2024Applicant: EM Microelectronic-Marin SAInventor: Fabien MALACARNE
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Publication number: 20240094772Abstract: A wearable device (1) including a case (2a, 2b) including a watertight compartment (26) containing a printed circuit board (5), the case (2a, 2b) being assembled to a strap (4a, 4b) for mounting this wearable device (1) on a body part of a user, said assembly of the case (2a, 2b) with the strap (4a, 4b) being configured so that a portion (7) of this strap (4a, 4b) includes at least one actionable part of the device (1).Type: ApplicationFiled: July 7, 2023Publication date: March 21, 2024Applicant: EM Microelectronic-Marin SAInventor: Fabien MALACARNE
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Patent number: 11934598Abstract: A displacement detection circuit (100) configured to implement a displacement detection method (500) for a pointing device (199) having at least one pixel array (190). The displacement detection circuit (100) includes at least one main calculator (110), at least one auxiliary calculator (111, 112, 113) at least one comparator (130) and at least one motion detector (150). The main calculator (110) is configured to calculate at least one main average (210) corresponding to the average of the at least one pixel array (190), which is compared to at least one auxiliary average (211, 212, 213) of the at least one auxiliary calculator (111, 112, 113). According to the result of the comparison, the at least one motion detector (150) indicates at least one direction (250) of displacement of the pointing device (199).Type: GrantFiled: December 21, 2022Date of Patent: March 19, 2024Assignee: EM MICROELECTRONIC-MARIN SAInventors: Jérôme Saby, Lorenzo Pierobon
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Patent number: 11932002Abstract: This disclosure relates to a sewing process of a breathable, reusable, and leak-proof garment multilayered-lining having absorbent, antimicrobial, waterproofing, and steam dispersion functions. Such lining aims at preventing body fluids such as sweat, blood, vaginal fluids, menstrual fluid, urine, breast milk, or post-surgical fluids from leaking. Such a lining provides the absorbent, antimicrobial, waterproofing, and steam dispersion functions. The lining may be sewed or adhered to the garment piece including: men's and women's underwear, shorts, short pants, skirts, pants, bras, shirts, T-shirts, jumpsuits, body shapers, dresses, men's and women's nightwear, etc. The sewing process creates channels for the liquid and creates a non-linear U-shaped structure on the lining to prevent leakage from the sides. The disclosed lining also has a reduced number of layers on its sides due to one of its layers being smaller in width than the other layers, making the coating thinner for the wearer.Type: GrantFiled: August 28, 2017Date of Patent: March 19, 2024Assignee: EC BRAND COM IMP EXP DE VEST EM GERAL LTDAInventor: Emily Steed Ewell
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Publication number: 20240088066Abstract: A semiconductor wafer (1a, 1b) including a plurality of chips (2) and a separation zone (3) spacing the semiconductor chips (2) from each other in this wafer (1a, 1b), such a separation zone (3) extending from a front face (4a) to an opposite backside face (4b) of this wafer (1a, 1b), this separation zone (3) includes a scribe line (6) configured to be diced using plasma etching and an inlet area (13) of this scribe line (6), the inlet (13) being delimitated by free ends of plasma etch-resistant material layers (9) extending each from a peripheral wall (20) of a functional part (18) of a chip (2) into the scribe line (6) by overlapping a top of a seal ring (7) of this chip (2).Type: ApplicationFiled: September 8, 2023Publication date: March 14, 2024Applicant: EM Microelectronic-Marin SAInventors: Christophe ENTRINGER, Yves Dupraz, Pierre Muller, Zeng Wang, Alexis Durand, Arthur Hugh MacDougall
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Patent number: 11927072Abstract: A valve for downhole chemical injection control, having a single chemical injection fluid line (2) to feed all the injection points, regardless of the number of zones, exclusively electrically-driven by a single electric cable (3), with embedded sensing electronics (7), which communicate and activate an electric motor (4), coupled to a multi-position sphere (5) for dosing the chemical injection fluid, which, according to the electric motor rotation, is moved, altering its position, to enable the passage of interest to be selected, according to the volume of chemical fluid to be injected, a single turn of the sphere being required to commute all the possible positions, the performance of which is low in power consumption, and for a short period of time, having after its positioning in the desired passage zero consumption to maintain this position.Type: GrantFiled: December 30, 2019Date of Patent: March 12, 2024Assignee: OURO NEGRO TECNOLOGIAS EM EQUIPAMENTOS INDUSTRIAIS S/AInventor: Leonardo Goncalves Candido Gomes
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Patent number: 11922137Abstract: A specification of a program code component module implementing a portion of a program application is received. A trained machine learning model is used to automatically predict to which one among a plurality of program architecture layer classifications the program code component module belongs. An automatic analysis option is selected based on the predicted program architecture layer classification for the program code component module. The selected automatic analysis option is performed on the program code component module.Type: GrantFiled: August 11, 2021Date of Patent: March 5, 2024Assignee: OutSystems—Software em Rede, S.A.Inventors: Hugo Miguel Ferrão Casal da Veiga, António Manuel de Carvalho dos Santos Alegria, Rui Valdemar Pereira Madaleno
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Patent number: D1034234Type: GrantFiled: December 2, 2022Date of Patent: July 9, 2024Assignee: EM CORPORATIONInventor: Han-Wook Park