Patents Assigned to Embedded Memory, Inc.
  • Method of reducing memory cell size for floating gate NAND flash
    Publication number: 20080061355
    Abstract: In accordance with the present invention, a new method, its structure and manufacturing method is described to reduce memory cell size about the half of the conventional method for a non-volatile NAND Flash cell. The control gates in a string of the NAND Flash cell array is formed as the combination of the drawn control gate and the self-aligned control gate by using a spacer method. The source and drain of a NAND cell is defined as the low doped region underneath the spacer.
    Type: Application
    Filed: March 1, 2007
    Publication date: March 13, 2008
    Applicants: Embedded Memory, Inc., Ace Memory, Inc.
    Inventor: David Choi
  • Method of reducing memory cell size for non-volatile memory device
    Publication number: 20080061358
    Abstract: In accordance with the present invention, a new method, its structure and manufacturing method is proposed to reduce memory cell size about the half of the conventional method for a non-volatile NAND Flash cell. The control gates in a string of the NAND Flash cell array is formed as the combination of the drawn control gate and the self-aligned control gate by using a spacer method. The source and drain of a NAND cell is defined as the low doped region underneath the spacer.
    Type: Application
    Filed: March 1, 2007
    Publication date: March 13, 2008
    Applicant: Embedded Memory, Inc.
    Inventor: David Choi