Abstract: The present invention introduces a sub-converter stage used in a pipelined analog-to-digital converter. The sub-converter stage comprises an amplifier with a gain A, a sub analog-to-digital converter with comparators and a digital unit, a first capacitor with capacitance C, a second capacitor with capacitance C??C, and customized reference signal Vrefk, where ? ? ? C C = 4 A + 2 and V refk = V ref ? ( 1 - ? ? ? C 2 ? C ) . If the gain A of the amplifier is adjustable, the sub-converter stage needs an error detector to detect the difference between the output of the amplifier and reference signal Vref and adjust the gain A of the amplifier. The present invention also introduces a pipelined analog-to-digital converter employing the sub-converter stage.

Abstract: The present invention introduces a sub-converter stage used in a pipelined analog-to-digital converter. The sub-converter stage comprises an amplifier with a gain A, a sub analog-to-digital converter with comparators and a digital unit, a first capacitor with capacitance C, a second capacitor with capacitance C??C, and customized reference signal Vrefk, where ? ? ? C C = 4 A + 2 and V refk = V ref ? ( 1 - ? ? ? C 2 ? C ) . If the gain A of the amplifier is adjustable, the sub-converter stage needs an error detector to detect the difference between the output of the amplifier and reference signal Vref and adjust the gain A of the amplifier. The present invention also introduces a pipelined analog-to-digital converter employing the sub-converter stage.

Abstract: The present invention relates to an analog-to-digital converter, especially to a pipelined analog-to-digital converter with calibration of capacitor mismatch and finite gain error. Comparing with the conventional pipelined analog-to-digital converter, the new analog-to-digital converter comprises more circuit blocks including an extra sub-converter stage, a control clock generator and an error detector, resulting in that each sub-converter stage has two operation modes: normal conversion mode and calibration mode. All of the sub-converter stages share one error detector which amplifies the output of the sub-converter stage in calibration mode. Furthermore, to store the output of the error detector, a memory is used in each sub-converter stage for controlling the gain of amplifier in order to make the error generated by the finite gain of amplifier and the error generated by the capacitance mismatch have the same size but opposite sign.

Abstract: The present invention relates to an analog-to-digital converter, especially to a pipelined analog-to-digital converter with calibration of capacitor mismatch and finite gain error. Comparing with the conventional pipelined analog-to-digital converter, the new analog-to-digital converter comprises more circuit blocks including an extra sub-converter stage, a control clock generator and an error detector, resulting in that each sub-converter stage has two operation modes: normal conversion mode and calibration mode. All of the sub-converter stages share one error detector which amplifies the output of the sub-converter stage in calibration mode. Furthermore, to store the output of the error detector, a memory is used in each sub-converter stage for controlling the gain of amplifier in order to make the error generated by the finite gain of amplifier and the error generated by the capacitance mismatch have the same size but opposite sign.