Abstract: An error correction code system for a memory for improving performance and testability. The parity columns of the memory array can be positioned centrally within the array to minimize routing distance to ECC logic circuitry. The parity columns can be grouped together or distributed throughout the array to optimize performance. A multiplexor circuit can be included for selectively coupling only the parity bits stored in the parity memory array to I/O circuitry. Therefore, the parity columns can be directly tested, and testing of the ECC logic circuitry is facilitated.

Abstract: Circuits and method for precharging a pair of complementary bitlines in a dynamic random access memory (DRAM). Both bitlines are precharged to VDD during a precharge phase, and during a sensing phase, the voltage of one of the pair of complementary bitlines is adjusted from VDD to a reference level. The reference level is generated by coupling the one of the pair of complementary bitlines to a capacitance means located within a reference voltage circuit. The reference voltage circuit can include one capacitor element or a plurality of capacitor elements connected in parallel with each other. Any number of the plurality of capacitor elements can be selectively enabled.