Abstract: Digital-to-analog converters (282, 292, 310, 340, or 370) produce intentionally nonlinear outputs. When outputs of a plurality of lower bits are replaced by a next higher bit, a downward step (281 or 330) is produced in an output voltage (276, 332, or 336). Each of the downward steps (281 or 330) results in production of substantially equal output voltages in response to two different digital numbers being inputted. The digital-to-analog converters (282, 292, 310, 340, or 370) of the present invention are useful in frequency-hopping oscillators (72, 136, 170, or 190), in phase-locked oscillators (10, 74, 152, 172, and 196), and in other electronic systems that include a learning path (222, 224, or 226) with a digital-to-analog converter.

Abstract: A phase locking oscillator (60, 70, 80, 90, or 110) and a radio frequency oscillator (62, 72, 82, 92, or 112) achieve reduced incidental frequency modulation. A frequency-deviation sensitivity is reduced by a divider (66 or 100) that reduces a frequency-control voltage, thereby decreasing voltage spikes and other electrical noise, and thereby reducing incidental frequency modulation. In embodiments having an AC voltage divider (66), the frequency-control voltage is reduced when a frequency thereof is above a predetermined roll-off frequency. Below the roll-off frequency, the voltage dividing function ceases, and full deviation sensitivity of the radio frequency oscillator (62, 72, or 82) is restored, whereby a capture range of the phase locking oscillator (60, 70, or 80) and a maximum frequency range of the radio frequency oscillator (62, 72, or 82) are restored.