Patents Assigned to EMPIRE TECHNOOGY DEVELOPMENT LLC
  • Patent number: 9524960
    Abstract: Technologies are generally described for increase of spacing between source and drain regions of a vertical high voltage transistor without a significant corresponding increase in the die size. In some examples, active silicon (at drain potential) may be removed at an edge of the die in the scribe grid so that the active silicon is approximately below a surface of the edge termination formed by a region of deep dielectric filled trenches. The recessed drain region at the edge of the die may increase a flashover distance without appreciably increasing the die size. Thus, a distance between the recessed drain region and the surface source region may be increased by a combination of vertical and lateral spacing resulting in a smaller overall die size and smaller parasitic capacitances when operated with substantially the same operating voltage.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: December 20, 2016
    Assignee: EMPIRE TECHNOOGY DEVELOPMENT LLC
    Inventor: Bishnu Gogoi
  • Patent number: 9466869
    Abstract: Mobile communication devices, e.g., cellphones, may integrate an antenna array that includes one or more antenna to form radio beams at a preferred direction and a signal locator to identify coordinates corresponding to a strongest signal strength and direct the antenna array towards the strongest single strength.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: October 11, 2016
    Assignee: EMPIRE TECHNOOGY DEVELOPMENT LLC
    Inventors: Li Tian, Xuefeng Yin