Abstract: A power converter circuit. In one aspect, the power converter circuit includes a first buck converter coupled in series to a second buck converter at a junction, and a control circuit coupled to each of the first and second buck converters. In another aspect, the control circuit is arranged to continuously operate the first buck converter, sense a voltage at the junction, compare the sensed voltage to a first threshold voltage and in response to the sensed voltage being at a voltage lower than the first threshold voltage disables the second buck converter. In yet another aspect, the control circuit is arranged to continuously operate the first buck converter, compare the sensed voltage to a second threshold voltage and in response to the sensed voltage being at a voltage higher than the second threshold voltage, the control circuit operates the second buck converter.

Abstract: A buck voltage converter is disclosed. The buck voltage generator includes a controller configured to generate one or more pulse width modulation (PWM) signals, and a plurality of serially connected switches configured to receive the PWM signals and to generate an output voltage signal at an output terminal based on the received PWM signals. The output voltage signal has an average voltage corresponding with a duty cycle of the PWM signals, a first switch of the plurality of serially connected switches has a first breakdown voltage and a second switch of the plurality of serially connected switches has a second breakdown voltage, and the first breakdown voltage is less than the second breakdown voltage.

Abstract: A power converter circuit is disclosed. In one aspect, the power converter circuit includes a first top buck converter circuit coupled in parallel to a second top buck converter circuit at a first connection node and at a second connection node, and a bottom buck converter circuit coupled in series to each of the first and second top buck converter circuits at the second connection node, a power input terminal coupled to the first and second top buck converter circuits, and a power output terminal coupled to the bottom buck converter circuit and to the first connection node.

Abstract: A power converter circuit. In one aspect, the power converter circuit includes a first buck converter coupled in series to a second buck converter at a junction, and a control circuit coupled to each of the first and second buck converters. In another aspect, the control circuit is arranged to continuously operate the first buck converter, sense a voltage at the junction, compare the sensed voltage to a first threshold voltage and in response to the sensed voltage being at a voltage lower than the first threshold voltage disables the second buck converter. In yet another aspect, the control circuit is arranged to continuously operate the first buck converter, compare the sensed voltage to a second threshold voltage and in response to the sensed voltage being at a voltage higher than the second threshold voltage, the control circuit operates the second buck converter.

Abstract: A multiphase switching converter includes: a plurality of phases, each phase including a current detection device, a set of switching devices, an output capacitor coupled to each phase of the plurality of phases, and a control circuit. The current detection device of each phase of the plurality of phases is configured to receive an error current from the control circuit and generate a corresponding signal to control a duty cycle of a set of corresponding switching devices such that each phase delivers a substantially equal quantity of charge to the corresponding output capacitor to maintain a charge balance on the corresponding output capacitor.

Abstract: A capacitance device includes: a semiconductor substrate; a capacitor disposed on the semiconductor substrate and including first and second positive terminals and first and second negative terminals; a passivation layer formed over the capacitor, the first and second positive terminals and the first and second negative terminals, the passivation layer defining first and second openings over the first and second positive terminals, respectively, a third opening over the first negative terminal and a fourth opening over the second negative terminal; a first metallic bump disposed on the passivation layer and including first extending portions that extend through each of the first and second openings, electrically coupling the first and second positive terminals; and a second metallic bump disposed on the passivation layer and including second extending portions that extend through each of the third and fourth openings, electrically coupling the first and second negative terminals.

Abstract: A power converter circuit is disclosed. In one aspect, the power converter circuit includes a power input terminal, a first output terminal and a second output terminal, a plurality of capacitors coupled to the power input terminal, the first output terminal and the second output terminal, a plurality of switches coupled to the plurality of capacitors and arranged to repetitively cycle the plurality of capacitors between a first configuration and a second configuration to generate a first output voltage at the first output terminal and a second output voltage at the second output terminal, and where the circuit is arranged to limit a maximum voltage applied to each of the plurality of capacitors and switches to a fraction of a voltage at the power input terminal.

Abstract: A power circuit is disclosed. The power circuit includes an input node, a plurality of inductors each connected to an output node, a plurality of phases each configured to provide current to one of the inductors, and a control circuit configured to trigger the phases. The phases are configured to provide current to one of the inductors in response to being triggered by the control circuit, the control circuit is configured to determine a variable time difference between a first phase being triggered and a second phase being triggered, and the time difference is based at least in part on a voltage difference between an input voltage at the input node and an output voltage at the output node.

Abstract: A power converter is disclosed. The power conveter includes a positive power supply, an output node, first, second, and third high side transistors serially connected between the positive power supply and the output node, and a high side bias voltage generator configured to generate a high side bias voltage. A gate of the second high side transistor is connected to the high side bias voltage generator. The power converter also includes a signal driver configured to selectively connect a gate of the first transistor to either the positive power supply or the high side bias voltage generator, a switch configured to selectively connect a gate of the third transistor to the high side bias voltage generator, and a capacitor connected to the gate of the third transistor and to a source of the second high side transistor.

Abstract: An electronic package comprises an integrated circuit (IC) configured to receive a power input signal and to deliver a regulated power output signal. A multilayer electrical routing structure is attached to the IC and is configured to couple the electronic package to an external circuit. The multilayer routing structure has one or more electrical conductors on each of at least two layers which are configured to route the power input signal from the external circuit to the IC and to route the regulated power output signal from the IC to the external circuit. The one or more electrical conductors form an integrated inductive device having a respective portion disposed on each of the at least two layers and the power output signal is coupled to the external circuit through the integrated inductive device.

Abstract: An electronic circuit is disclosed. The electronic circuit includes a switching circuit that includes a high side switch connected to a low side switch at a switch node, a controller arranged to generate a high side control signal and a low side control signal, a variable delay circuit arranged to receive the high side control signal and in response transmit a corresponding delayed high side control signal, and to receive the low side control signal and in response transmit a corresponding delayed low side control signal, a high side driver circuit arranged to transmit a high side drive signal to the high side switch in response to receiving the delayed high side control signal, and a low side driver circuit arranged to transmit a low side drive signal to the low side switch in response to receiving the delayed low side control signal.

Abstract: A multiphase switching converter includes: a plurality of phases, each phase including a current detection device, a set of switching devices, an output capacitor coupled to each phase of the plurality of phases, and a control circuit. The current detection device of each phase of the plurality of phases is configured to receive an error current from the control circuit and generate a corresponding signal to control a duty cycle of a set of corresponding switching devices such that each phase delivers a substantially equal quantity of charge to the corresponding output capacitor to maintain a charge balance on the corresponding output capacitor.

Abstract: A multiphase switching voltage regulator is disclosed. The regulator includes a first clock generator circuit configured to receive a reference clock, and to generate M first clocks, where the M first clocks are phase separated by 360°/M, a plurality of phase extrapolator circuits, where the plurality of phase extrapolator circuits includes N phase extrapolator circuits, and a phase selector multiplexer configured to provide one of the M first clocks to each of the phase extrapolator circuits, where the N phase extrapolator circuits are configured to generate N output clocks, where the N output clocks are phase separated by 360°/N.

Abstract: A power converter circuit is disclosed. In one aspect, the power converter circuit includes a power input terminal, a first output terminal and a second output terminal, a plurality of capacitors coupled to the power input terminal, the first output terminal and the second output terminal, a plurality of switches coupled to the plurality of capacitors and arranged to repetitively cycle the plurality of capacitors between a first configuration and a second configuration to generate a first output voltage at the first output terminal and a second output voltage at the second output terminal, and where the circuit is arranged to limit a maximum voltage applied to each of the plurality of capacitors and switches to a fraction of a voltage at the power input terminal.

Abstract: A power converter is disclosed. The power converter includes a positive power supply, an output node, first, second, and third high side transistors serially connected between the positive power supply and the output node, and a high side bias voltage generator configured to generate a high side bias voltage. A gate of the second high side transistor is connected to the high side bias voltage generator. The power converter also includes a signal driver configured to selectively connect a gate of the first transistor to either the positive power supply or the high side bias voltage generator, a switch configured to selectively connect a gate of the third transistor to the high side bias voltage generator, and a capacitor connected to the gate of the third transistor and to a source of the second high side transistor.

Abstract: An electronic circuit is disclosed. The electronic circuit includes a switching circuit that includes a high side switch connected to a low side switch at a switch node, a controller arranged to generate a high side control signal and a low side control signal, a variable delay circuit arranged to receive the high side control signal and in response transmit a corresponding delayed high side control signal, and to receive the low side control signal and in response transmit a corresponding delayed low side control signal, a high side driver circuit arranged to transmit a high side drive signal to the high side switch in response to receiving the delayed high side control signal, and a low side driver circuit arranged to transmit a low side drive signal to the low side switch in response to receiving the delayed low side control signal.

Abstract: A voltage regulator circuit is disclosed. The voltage regulator circuit includes a level shifter circuit. The level shifter circuit includes first and second nodes that each switch between a first low voltage and a first high voltage, third and fourth nodes that each switch between a second low voltage and a second high voltage, where the second high voltage is different from the first high voltage. The level shifter circuit also includes a DC path circuit connected between the first and third nodes, and arranged to selectively conduct a current between the first and third nodes.

Abstract: A buck voltage converter is disclosed. The buck voltage generator includes a controller configured to generate one or more pulse width modulation (PWM) signals, and a plurality of serially connected switches configured to receive the PWM signals and to generate an output voltage signal at an output terminal based on the received PWM signals. The output voltage signal has an average voltage corresponding with a duty cycle of the PWM signals, a first switch of the plurality of serially connected switches has a first breakdown voltage and a second switch of the plurality of serially connected switches has a second breakdown voltage, and the first breakdown voltage is less than the second breakdown voltage.

Abstract: A power circuit is disclosed. The power circuit includes an input node, a plurality of inductors each connected to an output node, a plurality of phases each configured to provide current to one of the inductors, and a control circuit configured to trigger the phases. The phases are configured to provide current to one of the inductors in response to being triggered by the control circuit, the control circuit is configured to determine a variable time difference between a first phase being triggered and a second phase being triggered, and the time difference is based at least in part on a voltage difference between an input voltage at the input node and an output voltage at the output node.

Abstract: An electronic package comprises an integrated circuit (IC) configured to receive a power input signal and to deliver a regulated power output signal. A multilayer electrical routing structure is attached to the IC and is configured to couple the electronic package to an external circuit. The multilayer routing structure has one or more electrical conductors on each of at least two layers which are configured to route the power input signal from the external circuit to the IC and to route the regulated power output signal from the IC to the external circuit. The one or more electrical conductors form an integrated inductive device having a respective portion disposed on each of the at least two layers and the power output signal is coupled to the external circuit through the integrated inductive device.