Abstract: A method of performing diadic operations in a processor is provided that includes receiving a first request packet initiating a read operation from a first memory address in the first request packet, and executing a first operation in the first request packet once the read request is completed. Also, the method includes generating a second request packet at a second memory address by combining the results of the first operation with the unused information in the first request packet. Furthermore, the method includes sending the second request packet to the Memory-Side Processor (MSP). When the MSP receives the second request, the MSP checks to determine if a write operation is requested and writes data to the second memory address, if a read operation is requested, the MSP reads data from the second memory address.

Abstract: A method of performing diadic operations in a processor is provided that includes receiving a first request packet initiating a read operation from a first memory address in the first request packet, and executing a first operation in the first request packet once the read request is completed. Also, the method includes generating a second request packet at a second memory address by combining the results of the first operation with the unused information in the first request packet. Furthermore, the method includes sending the second request packet to the Memory-Side Processor (MSP). When the MSP receives the second request, the MSP checks to determine if a write operation is requested and writes data to the second memory address, if a read operation is requested, the MSP reads data from the second memory address.

Abstract: A memory storage system is that includes a memory element having a memory address for a physical memory. A memory controller receives a command for accessing the memory element using a program-generated address and dynamically transforms the program-generated address into the memory address for the physical memory using a rotation module and configuration information. A data word accessed by the physical address is then provided to a set of arithmetic logic units (ALUs) where multiple computations are performed simultaneously so as top reduce program execution time and energy. The configuration information provided to the rotation unit configures the set of ALUs.

Abstract: A system for governing the spawning of a thread from a parent thread by an application in a processor is provided. The system includes a first multiplexor module that selects from one or more registers a policy used to spawn a thread, and makes the policy available for execution. A second multiplexor module selects one or more of the policy values used in a spawn process whose policy was selected by the output of the first multiplexor module, the second multiplexor module outputs a first signal indicative of the selected policy value to accompany the selected policy, which may be given to the child thread as its initial spawn count when the policy so indicates. A third multiplexor module selects either the first signal or a null where the selected policy value of the first signal is used to update the remaining thread credits of the thread's parent.

Abstract: A memory controller is provided that includes a host system interface that receives requests from applications and sends read or write commands to a disk for data retrieval. A threadlet core provides threadlets to the host system interface that enable the host system interface to use a logical bit address that can be sent to a memory device for execution without having to read and write entire blocks to and from the memory device.

Abstract: A topology for routing message traffic between interconnecting nodes of a network is provided that includes a plurality of rings having a plurality of interconnecting nodes. A number of trees include at least one leaf at a same relative position of the rings. The trees and the rings form a unique combination that provides superior network performance for moderate numbers of the interconnecting nodes, wherein each interconnecting node has only a limited ability to handle a plurality of links.

Abstract: A system and method for identifying from an address an appropriate target node and a location in that node that holds desired data related to that address is provided. The system and method includes a logical address generator that generates a logical address. The system and method includes a subspace index extraction module that extracts a subspace index from the logical address. The system and method includes a subspace configuration table that retrieves a plurality of parameters of the subspace index to locate the desired data.

Abstract: A topology for routing message traffic between interconnecting nodes of a network is provided that includes a plurality of rings having a plurality of interconnecting nodes. A number of trees include at least one leaf at a same relative position of the rings. The trees and the rings form a unique combination that provides superior network performance for moderate numbers of the interconnecting nodes, wherein each interconnecting node has only a limited ability to handle a plurality of links.