Abstract: Embodiments of the current invention permit a user to allocate cache memory to main memory more efficiently. The processor or a user allocates the cache memory and associates the cache memory to the main memory location, but suppresses or bypassing reading the main memory data into the cache memory. Some embodiments of the present invention permit the user to specify how many cache lines are allocated at a given time. Further, embodiments of the present invention may initialize the cache memory to a specified pattern. The cache memory may be zeroed or set to some desired pattern, such as all ones. Alternatively, a user may determine the initialization pattern through the processor.

Abstract: A FCP initiator sends a FCP write command to a FCP target within a second FC Exchange, and the target sends one or more FC write control IUs to the initiator within a first FC Exchange to request a transfer of data associated with the write command. The first and second FC exchanges are distinct from one another. A payload of each write control IU includes an OX_ID value with which the initiator originated the second Exchange and a RX_ID value assigned by the FCP target for the second exchange. The two Exchanges yield a full-duplex communication environment between the initiator and target that enables the reduction or elimination of latencies incurred in a conventional FCP write I/O operation due to the half-duplex nature of a single FC Exchange. The write control IU may be an enhanced FCP_XFER_RDY IU or a new FC IU previously undefined by the FCP standard.

Abstract: Disclosed herein is a method for improving Input/Output (I/O) performance in a host system having multiple CPUs. Under this method, various interrupt affinity schemes are provided, which associate multiple processors, interrupts, and I/O channels for sending the interrupts, thereby allowing the interrupts to be almost evenly loaded among the multiple I/O channels and processors. Also, data locality (“warm cache”) can be achieved through the interrupt affinity schemes that associate each interrupt to its source processor, namely, the processor originating the I/O request that results in the interrupt.

Abstract: A network device comprising a first attach point, a second attach point, a switch and persistent connection logic is provided. The first attach point may connect the network device to a first link, and the second attach point may connect the network device to a second link. The switch may connect the first attach point to the second attach point. The persistent connection logic may create a persistent connection between a first network element and a second network element, where the persistent connection comprises the network device, the first link and the second link. The network device may also implement a non-persistent connection between two network elements, where the non-persistent connection may comprises the network device.

Abstract: A method, network device and system for remote direct memory access (RDMA) over Converged Ethernet (RoCE) packet sequence acceleration are disclosed. The network device comprises one or more functionality components for communicating with a host system. The host system is configured for implementing a first set of functionalities of a network communication protocol, such as RoCE. The one or more functionality components are also operable to implement a second set of functionalities of the network communication protocol.

Abstract: One or more modules include a first portion that teams together multiple physical network interface ports of a computing system to appear as a single virtual network interface port to a switch to which the physical ports are linked. A second portion determines a receive port upon which a packet of a TCP session was received. A third portion assigns a transmit port to be the receive port, wherein the transmit port is used by the computing system to transmit packets of the TCP session. The third portion assigns the transmit port prior to a TCP offload engine (TOE) being enabled to offload from the system CPU processing of packets of the TCP session transceived on the assigned transmit/receive port. If a subsequent packet for the TCP session is received on a different second port, the transmit port is reassigned to be the second port.

Abstract: Methods and systems are provided for enabling existing or legacy network devices to recognize and parse packets defined in accordance with future-defined standards, without having to be re-configured to be compatible with such standards. A transmitting network device may generate packets such that to enable receiving network devices to bypass, when processing the packets, unknown or newly-inserted fields, such as tag headers, in the packets, and to continue processing the remainder of the packet. This may be achieved by, for example, incorporating in the packets, when such unknown or newly-inserted are included in the packets, corresponding indication fields (e.g., tag header type fields) which may indicated that the unknown or newly-inserted are inserted. Further, indication fields may enable a receiving device to skip over these unknown or newly-inserted. For example, each tag header type filed may be associated with a particular tag header length of the corresponding tag header.

Abstract: A system and method for adding error protection capability to a digital logic circuit, for example including random storage logic. Various aspects of the present disclosure, for example, comprise providing error protection against soft errors that occur during operation of digital logic circuitry.

Abstract: Methods and systems are provided for dynamically, adaptively and/or automatically managing performance metrics in infrastructures (e.g., network topologies). A network management device (e.g., datacenter server) may receive performance data relating to one or more performance metrics monitored in a managed infrastructure; and may determine for each performance metric, whether performance is acceptable or not, based on one or more performance parameters (e.g., thresholds) used in evaluating performance. The performance parameters may be set to allow for a plurality of acceptable performance criteria (e.g., expected mean, deviation, etc.). Further, the performance parameters may be set and/or adjusted dynamically and/or adaptively, such as to allow variations (e.g., time-based) in acceptable performance. Thus, determining whether performance is acceptable or unacceptable may be based on matching (e.g.

Abstract: Embodiments of the invention are directed to automatically populating a database of names and secrets in an authentication server by sending one or more lists of one or more names and secrets by a network management software to an authentication server. Furthermore, some embodiments provide that the lists being sent are encrypted and/or embedded in otherwise inconspicuous files.

Abstract: In one embodiment of the invention, a method for protecting a content addressable memory is disclosed. The method includes storing a marker bit associated with each data block stored in a random access memory (RAM), states of the marker bit representing whether the data block was recently read from the RAM or recently written into the RAM; receiving a client address pointing to a starting address of a data block stored in the RAM; comparing the client address against one or more addresses stored in a content addressable memory (CAM) to determine a hit indicating the client address was stored in the CAM or a miss indicating the client address was not stored in the CAM; and in response to a miss, the method further includes checking a state of the marker bit associated with the data block pointed to by the client address.

Abstract: A system and method for routing data is provided. The system includes a communication interface, a FIFO and a processor module. The communication interface may transmit or receive data. The FIFO is operable to buffer data that has been received by the communication interface. The FIFO is also operable to buffer data that will be transmitted from the communication interface. The processor module is connected to the FIFO and is operable to monitor for data, decode a route according to the data, and move data according to the route and the amount of data in the FIFO.

Abstract: This is directed to providing Fiber Channel over Ethernet communication. For example a Fiber Channel over Ethernet (FCoE) enabled device (such as a computer) may include a Fiber Channel over Ethernet Adapter (FCoEA). The FCoEA may include an HBA module. The HBA module may be configured to communicate over the Fiber Channel protocol. The FCoE enabled device may process and encapsulate the HBA module's communication in order to send them over an Ethernet network instead. The FCoE enabled device may process communications directed to various Fiber Channel fabric services by utilizing existing Ethernet services, such as an iSNS server. Thus, the FCoE enabled device can emulate a Fiber Channel network for the HBA module using the Ethernet network and one or more Existing Ethernet services/servers.

Abstract: A system and method for interconnecting physical channels is provided. The system includes a port containing an optical receiver, a port control module, a route determination module, and a connectivity module. The port control module is operably connected to a first physical channel to receive a Fiber Channel frame comprising data and a data header. The route determination module selects a route between the port control module and the second physical channel according to the data header. The connectivity module is operably connected to the port control module and to the route determination module. The connectivity apparatus may switch frames between the port control module and the second physical channel under control of the route determination module in order to transfer Fiber Channel frames to the second physical channel.

Abstract: A device, integrated circuit and method for generating simulated errors are disclosed. In the disclosed device, integrated circuit and method, an original data value is read from a memory. The original data value is intercepted by the integrated circuit. The integrated circuit is operable to virtualize an error in the original data value to generate a modified data value. The integrated circuit is also operable to generate an interrupt according to the virtualization. This disclosure may be particularly useful for high-level memory validation.

Abstract: Restoring retired transaction identifiers (TID) associated with Direct Memory Access (DMA) commands without waiting for all DMA traffic to terminate is disclosed. A scoreboard is used to track retired TIDs and selectively restore retired TIDs on the fly. DMA engines fetch a TID, and use it to tag every DMA request. If the request is completed, the TID can be recycled to be used to tag a subsequent request. However, if a request is not completed, the TID is retired. Retired TIDs can be restored without having to wait for DMA traffic to end. Any retired TID value may be mapped to a bit location inside a scoreboard. All processors in the system may have access to read and clear the scoreboard. Clearing the TID scoreboard may trigger a DMA engine to restore the TID mapped to that location, and the TID may be used again.

Abstract: A system and method for data communication is provided. The system includes a first port, a transmission layer module and a signaling layer module. The transmission layer module supports a first priority and a second priority. The signaling layer module can route data between the first port and a second port and can route data between the first port and a third port. The signaling layer module supports alternate routing if one or both of the second port and the third port fail.

Abstract: Snooping in SAS expander networks is disclosed. Ports in a SAS expander may include snoop circuitry and a snoop tap which allows snoop data to be diverted for snooping prior to any significant transformation of the traffic by the regular port logic. Furthermore, the snoop circuitry can receive OOB signaling and convert it to K characters for transmission through the SAS network and subsequent analysis by a protocol analyzer. The ports and cascades in the expander network can be configured to create snoop paths to enable snoop data to be passed through the network to locations where a protocol analyzer can be easily attached. With SAS snoop ports, there is no disruption to the system. Because only a copy of the data is routed to the analyzer, there is no change to the original signal path and latency is identical with or without the analyzer.

Abstract: A method for offloading Fiber Channel transmit data in an I/O operation. The transmit data includes Fiber Channel sequences, each Fiber Channel sequence includes multiple frames. The method includes generating a single transmit sequence request descriptor for transmitting all of the plurality of frames; creating an Ethernet header, a FCoE encapsulation header, and a Fiber Channel header for each frame in response to information in the transmit sequence request descriptor; creating start of frame and end of frame delimiters; inserting data into each frame; computing Fiber Channel CRC and Ethernet FCS for each frame; and transmitting the plurality of frames over a network. In each of the plurality of frames, the Ethernet header precedes the FCoE encapsulation header, which precedes the Fiber Channel header, which precedes the data. The data is followed by the Fiber Channel CRC, which is followed by the Ethernet FCS.

Abstract: Embodiments of the current invention permit a user to allocate cache memory to main memory more efficiently. The processor or a user allocates the cache memory and associates the cache memory to the main memory location, but suppresses or bypassing reading the main memory data into the cache memory. Some embodiments of the present invention permit the user to specify how many cache lines are allocated at a given time. Further, embodiments of the present invention may initialize the cache memory to a specified pattern. The cache memory may be zeroed or set to some desired pattern, such as all ones. Alternatively, a user may determine the initialization pattern through the processor.