Abstract: A real time data processing system in which each of a series of processing nodes is provided with its own data store partitioned into a first section reserved for the storage of data local to the respective node and a second section reserved for the storage of data to be shared between nodes. The nodes are interconnected by a data link and whenever a node writes to an address in the second section of a data store the written data is communicated to all of the nodes via the data link. The data in each address of the second sections of the data stores can be changed only by one respective processing node which acts as a master for that address. As each address containing shared data can only be written to by one node collisions between different nodes attempting to change a common item of data cannot occur.

Abstract: A system for coupling sets of plurality of nodes that are memory coupled to pass write only data memory to memory via a data link that further includes an optical fiber controller coupled to each data link. Each controller is interconnected through fiber for high speed data transfers from one set of nodes to another. The controller is capable of connection implementing three and four cable interfaces. The data is transmitted through the fiber serially but the controller is adapted to receive parallel data and convert to serial form and vice versa.

Abstract: A real time data processing system consisting of a plurality of processing nodes and a write only reflective data link for transferring information containing writes only between the plurality or processing nodes. All the nodes include a bus, a processor coupled to the bus, a memory having at least two ports with one port connected to the bus and the other port connected to the data link and a sensor for sensing a write to the memory. At least one node has a VMEbus as the bus and serves as an I/O connected to one port of the memory. Further a local bus included for inputting and outputting from the memory. The local bus is connected to a third port of the memory.

Abstract: A real time data processing system in which each of a series of processing nodes is provided with its own data store partitioned into a first section reserved for the storage of data local to the respective node and a second section reserved for the storage of data to be shared between nodes. The nodes are interconnected by a data link and whenever a node writes to an address in the second section of a data store the written data is communicated to all of the nodes via the data link. The data in each address of the second sections of the data stores can be changed only by one respective processing node which acts as a master for that address. As each address containing shared data can only be written to by one node collisions between different nodes attempting to change a common item of data cannot occur.

Abstract: An advance polling bus arbiter includes a priority selector for selecting during a polling cycle a highest priority source system unit which is seeking access to a system bus. Bus grant logic sends the highest priority source system a bus grant signal which indicates that the selected system unit can make a transfer during the next cycle. An advance link logic unit compares a target bus address received from the selected system unit to a local bus address and simultaneously signals an intersystem bus link of an impending intersystem transfer while the source system unit is receiving its bus grant signal.

Abstract: A real time data processing system in which each of a series of processing nodes is provided with its own data store partitioned into a first section reserved for the storage of data local to the respective node and a second section reserved for the storage of data to be shared between nodes. The nodes are interconnected by a data link and whenever a node writes to an address in the second section of a data store the written data is communicated to all of the nodes via the data link. The data in each address of the second sections of the data stores can be changed only by one respective processing node which acts as a master for that address. As each address containing shared data can only be written to by one node collisions between different nodes attempting to change a common item of data cannot occur.