Abstract: A frequency synthesizer or portion thereof, that includes only one main phase-locked loop. The phase-lock loop includes a digital divider that can effectively divide in fractions, thus, permitting use of a higher reference frequency than normally required for the same degree of frequency resolution in integer divisor synthesizers. This, in turn, increases the short-term stability and reduces phase-noise. The fractional divider includes a secondary phase-lock loop that tends to introduce an unwanted ramp signal which causes spurious sidebands in the output signal. These spurious sidebands, when objectionable, are effectively suppressed by a circuit that generates a second ramp signal of similar frequency, duration and shape to the unwanted ramp signal but of opposite phase.