Abstract: A front-end used for processing communication signals in a received path including an antenna cable segment that receives the communication signals. A RF segment provides mixing and filtering of the received signals, the RF segment outputs a first set of signals. An analog baseband segment performs low pass filtering and digitizes the first set of signals in order to input a second set of signals for further processing. The RF segment and the analog baseband segment includes a selective set of components that are power programmable, such that the power consumption of the selective set of components are controlled by bias currents delivered to each of the selective components. In another embodiment, the components of a transmit path are also power programmable via bias current. In another embodiment, the ADCs and DACs of a receive and transmit paths are power programmable via bias current and reconfigurable blocks of ADC and DAC cores.

Abstract: The present invention allows multi-channel communications equipment to detect and eliminate a false interpretation of interference as a valid signal. The solution is based on the observation that the simultaneous arrival of energy on two independent channels is an impossible event. So, when such an event happens, it is a reliable signature of confusing out-of-band energy for a valid signal.

Abstract: The present invention dramatically reduces dynamic mismatches between the different current segments of a segmented current-mode DAC. By providing substantially the same local architecture for each of the individual current segments, parasitic effects of any physical realization can be controlled. In one embodiment, the most-significant-bit (MSB) current segments and the least-significant-bit (LSB) current segments each have the same number of multiple internal current branches. In the MSB segments, the multiple internal current branches are combined at a source node; whereas, in the LSB segment, a portion of the segment current is dumped, or wasted, through at least some of the internal current branches.

Abstract: The linearity of switched-capacitor, pipeline digital to analog converters is improved by balancing the settling behavior of its pre-charge switches. In more detail, a switched capacitor DAC includes a number of substantially identical cells, one cell for each bit of an input digital word. A number of switch driver circuits are used to apply respective switch control signals to turn respective switches on and off. Advantageously, the switch control signals differ by an amount determined to equalize the gate-to-source voltage difference between different switches.

Abstract: A rate-converting, low-latency, low power interleaver architecture is implemented using block read-write methods. The memory architecture is such that it allows multiple input bits to be written into memory simultaneously. In some embodiments, the number of simultaneous bits written into memory corresponds to an error encoding rate, such that an encoder and interleaver can operate within the same clock domain, regardless of the code rate. The memory architecture also allows an entire row of interleaved data to be read out in one clock cycle.

Abstract: An analog buffer with low harmonic distortion and low power supply voltage buffers a signal with wide voltage swing. The lower output voltage swing is increased, by adding a voltage level shifter to the feedback path of a servo. The upper output voltage swing is increased by coupling the output load to Vdd.

Abstract: Upon a triggering event, a delay chain shifts data out at a higher rate than incoming packets and a processor controls bypassing circuitry to reduce the latency of hardware implementations of, for example, 802.11a OFDM receivers, with long delay chains. The signal processing algorithms used to recover symbol timing need a large number of samples stored in a delay chain, often consisting of pipelined registers. Such a delay chain introduces a large lag between the time samples have been acquired by the data converters and the time they are processed. This delay makes it difficult for higher level network layer implementations to meet the deadlines of 802.11a WLAN protocol. The proposed scheme implements dynamic reduction in the depth of the delay chain once timing recovery has been performed. A multi-step scheme achieves exponential reduction in the number of elements in the delay chain in every step.

Abstract: A base bias circuit generates a bias voltage for a bipolar transistor. The base bias circuit includes a current mirror circuit which tracks current through a current source which drives emitter current through the bipolar transistor. A primary biasing bipolar transistor and a secondary bipolar transistor have a &bgr; which tracks the &bgr; of the bipolar transistor. The primary biasing bipolar transistor receives current from the current source through a current mirror circuit to develop the bias voltage. A bias resistor coupled between the bias voltage and the base of the primary biasing bipolar transistor tracks resistance variations in the base resistor. The secondary biasing transistor tracks changes in base current to the bipolar transistor and supplies additional current to the primary biasing transistor to compensate for changes in &bgr;.

Abstract: Using a combination of auto-correlation and cross-correlation techniques provides a symbol timing recovery in a Wireless Local Area Network (WLAN) environment that is extremely robust to wireless channel impairments such as noise, multi-path and carrier frequency offset. An auto-correlator provides an estimate for a symbol boundary, and a cross-correlator is subsequently used to more precisely identify the symbol boundary. Peak processing of the cross-correlation results provides further refinement in symbol boundary detection. In receiving a packet conforming to the IEEE 802.11a standard, the method requires a minimum of only three short symbols of the 802.11a short preamble to determine timing, and guarantees timing lock within the duration of the 802.11a short preamble. This method and system can be easily applied to any other preamble based system such as 802.11g and High Performance Radio LAN/2 (HIPERLAN/2).

Abstract: The invention relates to using a shift-and-add technique with a group of pre-calculated angles, such as the Coordinated Rotation Digital Computer (CORDIC) algorithm, in a hardware efficient digital carrier offset compensation loop. The implementation uses the shift-and-add technique for an efficient arctangent structure calculating phase offset errors. The implementation optionally uses the shift-and-add technique as a Numerically Controlled Oscillator (NCO) to track and compensate for a phase shift.

Abstract: A digital-to-analog converter (DAC) with high linearity includes a switched capacitor amplifier removably coupled to a capacitor array. The result of the conversion by the capacitor array is sampled by the switched capacitor amplifier directly from the capacitor in the most significant cell in the array. The switched capacitor amplifier includes a memory capacitor and a feedback capacitor. The memory capacitor provides the initial output voltage corresponding to the result of the conversion when coupled to the capacitor array and stores the output voltage while the feedback capacitor is reset.

Abstract: The invention relates to a novel methodology and apparatus for clock-offset compensation and common-phase offset correction in Frequency Division Multiplixing based wireless local area network (WLAN) environment, such as an Orthogonal Frequency Division Multiplexing (OFDM) environment. A curve fit, such as a threshold-based, least mean squares (LMS) fit of phase of the pilot sub-carriers in each OFDM symbol is used to estimate and counteract the rotation of the data sub-carriers due to residual frequency offset, low frequency phase noise, and clock offset. The invention is particularly well suited to wireless channels with multipath where pilots typically undergo frequency-selective fading. The thresholding LMS is implemented in a hardware-efficient manner, offering cost advantages over a weighted-LMS alternative. Additionally, the invention uses a unique phase-feedback architecture to eliminate the effects of phase wrapping, and avoid the need to refine channel estimates during packet reception.

Abstract: A unified digital front end filtering circuit is described for IEEE 802.11g protocol compliant systems. The front end uses polyphase rate conversion filters cascaded with channel extraction and pulse shaping filters to accommodate the different sampling rate requirements for orthogonal frequency division multiplexing (OFDM) and direct sequence spread spectrum (DSSS) modulation, which have to be supported simultaneously, without using separate analog front ends.

Abstract: A Channel Association method and apparatus for a wireless Network increases data throughput by intelligently associating clients to channels. Data rates are assigned to channels and clients with a similar data rate are associated to the same channel. The association is based on the client's distance from a host, the received power of each client and the performance of the client at the host.

Abstract: A programmable hardware architecture and design methodology for the implementation of a sample rate conversion engine is presented. The conversion engine supports scalable filter taps and can be tuned to a range of interpolation and decimation requirements. The conversion engine can be used effectively in wideband systems to efficiently extract and process digital sequences with protocol specific sampling rate requirements. The conversion engine can also be used as a hardware accelerator for software defined radios and communication systems that require adaptive sampling rates.

Abstract: A digital-to-analog converter (DAC) with high linearity includes a switched capacitor amplifier removably coupled to a capacitor array. The result of the conversion by the capacitor array is sampled by the switched capacitor amplifier directly from the capacitor in the most significant cell in the array. The switched capacitor amplifier includes a memory capacitor and a feedback capacitor. The memory capacitor provides the initial output voltage corresponding to the result of the conversion when coupled to the capacitor array and stores the output voltage while the feedback capacitor is reset.

Abstract: An analog buffer with low harmonic distortion and low power supply voltage buffers a signal with wide voltage swing. The lower output voltage swing is increased, by adding a voltage level shifter to the feedback path of a servo. The upper output voltage swing is increased by coupling the output load to Vdd.

Abstract: A method and circuit structure scale the power consumption of a current mode digital/analog converter (DAC) in proportion to performance parameters, such as sampling speed (i.e., clock samples per second) and resolution (number of bits) under programmable control. In one embodiment, a current mode segmented DAC provided approaches the performance of custom implementations designed for specific combinations of these parameters, across a wide range of such parameters by varying current relative to the sampling rate and the resolution and by selectively enabling current sources in the DAC.

Abstract: A method for implementing segmented digital-analog converters (DACs) operating in the current mode matches the time constants in the most-significant-bit (MSB) segments to the time constants in the (LSB) least-significant-bit segments, and any intermediate-significant-bit (ISB) segments. The method can be implemented using the simple addition of capacitances or the resizing of transistors in the circuit at appropriate points. The resulting DAC exhibits high dynamic linearity and spurious free dynamic range (SFDR).

Abstract: A sample and hold circuit including a capacitor is charged to a sample voltage from an open loop circuit such as a transistor circuit controlled by an input voltage. The sample voltage on the capacitor is converted to a digital signal via an ADC (Analog to Digital Converter). A digital correction circuit compensates for differences in voltage between the sample voltage on the capacitor and the input voltage based on properties of the open loop circuit and successive sample voltages on the capacitor. Consequently, nonlinearities can be compensated so that use of an open loop circuit or transistor circuit is less likely to negatively impact an overall accuracy of the ADC device.