Patents Assigned to .Engineering, Inc.
  • Publication number: 20240154642
    Abstract: The present disclosure provides an electronic module including a circuit including a transmitting part and a receiving part physically separated from the transmitting part. The electronic module also includes an element isolated from the circuit and configured to block electrical interference between the transmitting part and the receiving part.
    Type: Application
    Filed: January 16, 2024
    Publication date: May 9, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Shih-Wen LU, Chun-Jen CHEN, Po-Hsiang TSENG, Hsin-Han LIN, Ming-Lun YU
  • Publication number: 20240155758
    Abstract: An electronic device is provided. The electronic device includes a first dielectric layer, an electronic element, an encapsulant, and a second dielectric layer. The first dielectric layer has a first coefficient of thermal expansion (CTE). The electronic element is disposed over the first dielectric layer. The encapsulant encapsulates the electronic element and has a second CTE. The second dielectric layer is disposed over the encapsulant and having a third CTE. The second CTE ranges between the first CTE and the third CTE.
    Type: Application
    Filed: November 4, 2022
    Publication date: May 9, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien Lin CHANG CHIEN, Yuan-Chun TAI, Yu Hsin CHANG CHIEN, Chiu-Wen LEE, Chang Chi LEE
  • Publication number: 20240153920
    Abstract: An electronic device is disclosed. The electronic device includes a first conductive plate and a first electronic component. The first conductive plate includes a first connecting portion. The first electronic component supports the first conductive plate through the first connecting portion. The first connecting portion is electrically connected to the first electronic component and configured to buffer stress from the first conductive plate to the first electronic component.
    Type: Application
    Filed: November 9, 2022
    Publication date: May 9, 2024
    Applicants: Advanced Semiconductor Engineering, Inc., UNIVERSAL SCIENTIFIC INDUSTRIAL (SHANGHAI) CO., LTD.
    Inventors: Yi-Hung HOU, Yung-Fa CHEN, Sheng-Chia CHEN
  • Patent number: 11977007
    Abstract: Siloxane compounds are removed from the atmospheres by silica supporting an organic sulfonic acid compound. The silica with the organic sulfonic acid compound has a specific surface area down to 500 m2/g and up to 750 m2/g and a pore volume down to 0.8 m3/g and up to 1.2 m3/g, both measured by nitrogen gas adsorption method and has a pore diameter down to 4 nm and up to 8 nm, at the peak of differential pore volume measured by nitrogen gas adsorption method. The durability of gas sensing element against siloxanes is improved.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: May 7, 2024
    Assignees: FIGARO ENGINEERING INC., NEW COSMOS ELECTRIC CO., LTD., UNIVERSITY PUBLIC CORPORATION OSAKA
    Inventors: Masato Takeuchi, Junpei Furuno, Kenta Fukui, Kenichi Yoshioka, Tatsuya Tanihira, Masakazu Sai, Takafumi Taniguchi, Hirokazu Mitsuhashi
  • Patent number: 11978706
    Abstract: An electronic package structure, an electronic substrate, and a method of manufacturing an electronic package structure are provided. The electronic package structure includes a substrate. The substrate includes a bonding region and an alignment structure. The bonding region is located at a side of the substrate and configured to bond with an electronic component. The alignment structure is located at the side of the substrate and out of the bonding region and configured to providing a fiducial mark for position-aligning, wherein the alignment structure comprises a first region and a second region visually distinct from the first region.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: May 7, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Shun-Tsat Tu, Pei-Jen Lo
  • Patent number: 11976915
    Abstract: There is described a method for interrogating optical fiber comprising fiber Bragg gratings (“FBGs”), using an optical fiber interrogator. The method comprises (a) generating an initial light pulse from phase coherent light emitted from a light source, wherein the initial light pulse is generated by modulating the intensity of the light; (b) splitting the initial light pulse into a pair of light pulses; (c) causing one of the light pulses to be delayed relative to the other of the light pulses; (d) transmitting the light pulses along the optical fiber; (e) receiving reflections of the light pulses off the FBGs; and (f) determining whether an optical path length between the FBGs has changed from an interference pattern resulting from the reflections of the light pulses.
    Type: Grant
    Filed: December 1, 2022
    Date of Patent: May 7, 2024
    Assignee: Hifi Engineering Inc.
    Inventors: Brian H. Moore, Walter Jeffrey Shakespeare, Phillip William Wallace, Viet Hoang, Chris Henrikson, Ajay Sandhu, Adrian Dumitru, Thomas Clement, Dongliang Huang, Seyed Ehsan Jalilian
  • Publication number: 20240145319
    Abstract: A semiconductor device package includes a supporting element, a transparent plate disposed on the supporting element, a semiconductor device disposed under the transparent plate, and a lid surrounding the transparent plate. The supporting element and the transparent plate define a channel.
    Type: Application
    Filed: January 2, 2024
    Publication date: May 2, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Tsung-Yu LIN, Pei-Yu WANG, Chung-Wei HSU
  • Publication number: 20240145941
    Abstract: The present disclosure relates to an electronic device that includes a first radiating element configured to radiate a first electromagnetic wave and a second radiating element configured to radiate a second electromagnetic wave. A first radiation pattern of the first electromagnetic wave is configured to be adjusted, and a second radiation pattern of the second electromagnetic wave is configured to be fixed.
    Type: Application
    Filed: January 9, 2024
    Publication date: May 2, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Shih-Wen LU
  • Publication number: 20240139674
    Abstract: An apparatus and a method are provided for a heating, ventilation, and air conditioning (HVAC) system air filter for a building ventilation system. The HVAC system air filter comprises a supportive frame configured to orient the HVAC system air filter within the building ventilation system. A composite filter medium retained within the supportive frame comprises a cotton gauze portion and an electrostatic portion. The cotton gauze portion is configured for treatment with a filter oil composition to enhance airflow and filtration of air flowing through the composite filter medium. The electrostatic portion is configured to electrostatically attract and agglomerate airborne molecular contaminants and volatile organic compounds (VOCs) as small as 0.001 microns in diameter. In some embodiments, the composite filter medium comprises substances configured to release a fragrance into air passing through the composite filter medium.
    Type: Application
    Filed: January 9, 2024
    Publication date: May 2, 2024
    Applicant: K&N ENGINEERING, INC.
    Inventors: Steve R. Williams, Jere James Wall
  • Publication number: 20240145357
    Abstract: The present disclosure provides an electronic assembly including a semiconductor device package. The semiconductor device package includes a first package and a conductive element. The first package includes an electronic component and a protection layer covering the electronic component. The conductive element is supported by the protection layer and electrically connected with the electronic component through an electrical contact. A method for manufacturing a semiconductor device package is also provided in the present disclosure.
    Type: Application
    Filed: January 2, 2024
    Publication date: May 2, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chang-Lin YEH, Jen-Chieh KAO
  • Publication number: 20240142727
    Abstract: An optoelectronic device includes a photonic component. The photonic component includes an active side, a second side different from the active side, and an optical channel extending from the active side to the second side of the photonic component. The optical channel includes a non-gaseous material configured to transmit light.
    Type: Application
    Filed: January 9, 2024
    Publication date: May 2, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jr-Wei LIN, Sin-Yuan MU, Chia-Sheng CHENG
  • Publication number: 20240140785
    Abstract: A method of attaching a film is provided. The method includes providing a carrier tape. The carrier tape supports a film over a surface of the carrier tape. The method further includes moving the film to a position over an electronic device. The method further includes attaching the film to the electronic device.
    Type: Application
    Filed: October 26, 2022
    Publication date: May 2, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Chin-Song LEE
  • Patent number: 11973018
    Abstract: An electronic package is provided. The electronic package includes a power regulating component, an electronic component, and a circuit structure. The circuit structure separates the power regulating component and the electronic component. The circuit structure is configured to provide a first power to the power regulating component. The power regulating component is configured to provide a second power to the electronic component through the circuit structure.
    Type: Grant
    Filed: February 9, 2022
    Date of Patent: April 30, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chiung-Ying Kuo, Hung-Chun Kuo
  • Patent number: 11973048
    Abstract: A semiconductor package includes a first die having a first surface, a first conductive bump over the first surface and having first height and a first width, a second conductive bump over the first surface and having a second height and a second width. The first width is greater than the second width and the first height is substantially identical to the second height. A method for manufacturing the semiconductor package is also provided.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: April 30, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: An-Nong Wen, Ching-Han Huang, Ching-Ho Chang
  • Patent number: 11973036
    Abstract: A method of manufacturing a semiconductor package structure is provided. The method includes providing a first carrier, forming a patterned buffer layer over the first carrier, forming a first redistribution structure that includes forming a first dielectric layer on the patterned buffer layer, after an electrical testing by applying an electric signal towards the first redistribution structure, removing the first carrier, removing portions of the first dielectric layer, resulting in a patterned first dielectric layer, the patterned first dielectric layer exposing portions of the first circuit layer, removing the exposed portions of the first circuit layer, using the patterned first dielectric layer as a mask, resulting in a patterned first circuit layer, and forming an electric conductor in a recess defined by the patterned first dielectric layer and the patterned first circuit layer.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: April 30, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Ting-Yang Chou
  • Patent number: 11973039
    Abstract: A semiconductor device package includes a semiconductor die, a first conductive element, a second conductive element, a metal layer, and a first redistribution layer (RDL). The semiconductor die includes a first surface and a second surface opposite to the first surface. The first conductive element is disposed on the second surface of the semiconductor die. The second conductive element is disposed next to the semiconductor die. The metal layer is disposed on the second conductive element and electrically connected to the second conductive element. The first RDL is disposed on the metal layer and electrically connected to the metal layer.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: April 30, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chia-Hao Sung, Hsuan-Yu Chen, Yu-Kai Lin
  • Patent number: 11967559
    Abstract: An electronic package is provided. The electronic package includes a semiconductor substrate. The semiconductor substrate includes a first active region and a first passive region separated from the first active region. The first active region is configured to regulate a power signal. The first passive region is configured to transmit a data signal.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: April 23, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chang Chi Lee, Chiu-Wen Lee, Jung Jui Kang
  • Patent number: 11967434
    Abstract: A multiple fluid model tool for multi-dimensional fluid modeling of a biological structure is presented. For example, a system includes a modeling component, a machine learning component, and a three-dimensional health assessment component. The modeling component generates a three-dimensional model of a biological structure based on multi-dimensional medical imaging data. The machine learning component predicts one or more characteristics of the biological structure based on input data and a machine learning process associated with the three-dimensional model. The three-dimensional health assessment component that provides a three-dimensional design environment associated with the three-dimensional model. The three-dimensional design environment renders physics modeling data of the biological structure based on the input data and the one or more characteristics of the biological structure on the three-dimensional model.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: April 23, 2024
    Assignee: Altair Engineering, Inc.
    Inventors: Zain S. Dweik, Shane Cline
  • Patent number: D1023736
    Type: Grant
    Filed: October 27, 2022
    Date of Patent: April 23, 2024
    Assignee: FLEECE PERFORMANCE ENGINEERING, INC.
    Inventors: Brayden Fleece, Matthew Miller
  • Patent number: D1025132
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: April 30, 2024
    Assignee: Velossa Tech Engineering Inc.
    Inventor: Dan Joseph Becker