Patents Assigned to ENI
  • Patent number: 5651865
    Abstract: Pulses of positive voltage are applied to the target of a dc sputtering process to create a reverse bias. This charges insulating deposits on the target to the reverse bias level, so that when negative sputtering voltage is reapplied to the target, the deposits will be preferentially sputtered away. The reverse bias pulses are provided at a low duty cycle, i.e., with a pulse width of 0.25-3 microseconds at a pulse rate of about 40-100 KHz. This technique reduces sources for arcing during a reactive sputtering process.
    Type: Grant
    Filed: June 17, 1994
    Date of Patent: July 29, 1997
    Assignee: ENI
    Inventor: Jeff C. Sellers
  • Patent number: 5584974
    Abstract: A dc sputtering process applies a pulsating dc voltage in which each cycle includes a pulse portion of negative dc voltage of -300 to -700 volts alternating with a reverse bias (positive) pulse of about +50 to +300 volts. The reverse bias pulse portion will reduce or eliminate sources for arcing in most cases. To combat sticky or persistent arcing, the negative pulse portion is monitored. If, during a window portion of the negative pulse portion, the applied voltage drops into a range characteristic of arcing for two successive cycles, then the applied power is interrupted for a period, e.g., 200 microseconds, and reverse bias is applied. An overvoltage detection and clamping circuit monitors the applied voltage for extreme voltage excursions, and if an overvoltage threshold is exceeded for two successive cycles, the applied power is interrupted. The overvoltage detection and clamping circuit can comprise a string of zener diodes or equivalent voltage limiting devices connected to the applied voltage.
    Type: Grant
    Filed: October 20, 1995
    Date of Patent: December 17, 1996
    Assignee: ENI
    Inventor: Jeff C. Sellers
  • Patent number: 5477188
    Abstract: A linear RF power amplifier employs push-pull pairs of high voltage mosfets. A minimum of transformers is employed, with an impedance matching transformer feeding an input balun supplying the input signal in push-pull to the gates of the mosfets. The drains are coupled to balanced legs of an output balun, followed by an output impedance matching transformer. Thermal sensors are employed for control of gate bias and also for control of drain voltage. The temperature sensors are mounted in the air inlet path and on the spreader plate of the heat sink. An aluminum or fiberglass strap is used to press the transistors against the spreader plate thereby ensuring good thermal contact with the transistor dies.
    Type: Grant
    Filed: July 14, 1994
    Date of Patent: December 19, 1995
    Assignee: ENI
    Inventors: Yogendra K. Chawla, Leonid Reyzelman