Patents Assigned to ENI
-
Patent number: 5810982Abstract: Pulses of a positive voltage are superimposed onto negative dc sputtering current that is applied to the target of a dc sputtering process to create a reverse bias. This charges insulating deposits on the target to the reverse bias level, so that when negative sputtering voltage is reapplied to the target, the deposits will be preferentially sputtered away. The reverse bias pulses are provided at a low duty cycle, i.e., with a pulse width of 0.25 to 3 microseconds at a pulse rage of 40 to 200 KHz. This technique reduces or eliminates the sources for arcing. A circuit arrangement for reverse biasing provides the forward (negative) dc sputtering power as a current source, and provides the pulses of reverse (positive) voltage as a voltage source.Type: GrantFiled: September 30, 1996Date of Patent: September 22, 1998Assignee: ENI Technologies, Inc.Inventor: Jeff C. Sellers
-
Patent number: 5770922Abstract: An RF probe for a plasma chamber picks up current and voltage samples of the RF power applied to an RF plasma chamber, and the RF voltage and current waveforms are supplied to respective mixers. A local oscillator supplies both mixers with a local oscillator signal at the RF frequency plus or minus about 15 KHz, so that the mixers provide respective voltage and current baseband signals that are frequency shifted down to the audio range. The phase relation of the applied current and voltage is preserved in the baseband signals. These baseband signals are then applied to a stereo, two-channel A/D converter, which provides a serial digital signal to a digital signal processor or DSP. A local oscillator interface brings a feedback signal from the DSP to the local oscillator. The DSP can be suitably programmed to obtain complex Fast Fourier Transforms of the voltage and current baseband samples.Type: GrantFiled: July 22, 1996Date of Patent: June 23, 1998Assignee: ENI Technologies, Inc.Inventors: Kevin S. Gerrish, Daniel F. Vona, Jr.
-
Patent number: 5770023Abstract: An asymmetric bipolar plasma etching process is employed for etching a workpiece positioned within a plasma chamber, to prepare the workpiece for a subsequent coating process. The etching process involves applying a negative high voltage to the workpiece, relative to an anode portion of the chamber. Pulses of a positive voltage are applied to the workpiece at a predetermined pulse width and a predetermined level relative to the anode, so that the applied voltage appears as a train of asymmetric bipolar pulses. The waveform has a major negative-going portion and a minor positive-going portion. The negative-going portion can have a voltage of minus 300 to minus 4,000 volts, and the positive-going pulses can have a voltage of plus 50 to plus 300 volts, and a typical pulse width between about 0.25 and 3 microseconds. The etching process can be followed by a sputter coating process in the same chamber. Another coating technique could also be used.Type: GrantFiled: February 12, 1996Date of Patent: June 23, 1998Assignee: ENI A Division of Astec America, Inc.Inventor: Jeff C. Sellers
-
Patent number: 5737169Abstract: A protective circuit for a power field effect transistor, e.g., a power MOSFET, employs a diode-switched pickup circuit, a threshold detector, and a timer. The pickup circuit includes a resistor and diode in series, with the diode connected with the MOSFET drain electrode and the resistor connected with the gate driver for the MOSFET gate electrode. A pickup voltage V.sub.1 appears at the junction of the diode and resistor. When the MOSFET is conducting the pickup voltage is the sum of the channel voltage V.sub.ds-on and the diode forward voltage V.sub.f. When the MOSFET is biased OFF, the pickup voltage is zero. The threshold detector compares the pickup voltage with a reference voltage that is offset some predetermined amount from the source electrode voltage. When threshold circuit goes high, the timer circuit provides a time-out or inhibit signal to an inhibit input of the gate driver circuit. Under high load current or high temperature conditions, the drain-source voltage V.sub.Type: GrantFiled: February 28, 1996Date of Patent: April 7, 1998Assignee: ENI, A Division of Astec America, Inc.Inventor: Jeff C. Sellers
-
Patent number: 5726603Abstract: A linear RF power amplifier employs push-pull pairs of high voltage mosfets. A minimum of transformers is employed, with an impedance matching transformer feeding an input balun supplying the input signal in push-pull to the gates of the mosfets. The drains are coupled to balanced legs of an output balun, followed by an output impedance matching transformer. Thermal sensors are employed for control of gate bias and also for control of drain voltage. The temperature sensors are mounted in the air inlet path and on the spreader plate of the heat sink. An aluminum or fiberglass strap is used to press the transistors against the spreader plate thereby ensuring good thermal contact with the transistor dies.Type: GrantFiled: February 14, 1997Date of Patent: March 10, 1998Assignee: ENI Technologies, Inc.Inventors: Yogendra K. Chawla, Leonid Reyzelman
-
Patent number: 5717293Abstract: A strike enhancement circuit for a dc power supply, which can be a switched half-bridge supply, creates a high voltage at high impedance to initiate a plasma in a plasma chamber or sputtering chamber. The strike circuit has a plurality of diode bridges that act as full-wave rectifiers or peak detectors. The transformer secondary of the power supply is connected through isolation capacitors to the ac inputs of each of the diode bridges. The dc ports of the diode bridges are stacked in series, and the combined, stacked voltage is applied across the input terminals of the plasma chamber. Each diode bridge also has a storage capacitor connected between the positive and negative dc ports. Positive and negative voltage peaks from the transformer secondary waveform are stored in the storage capacitors. The combined dc outputs applied to the plasma chamber appear as a voltage high enough to initiate a plasma discharge.Type: GrantFiled: February 24, 1997Date of Patent: February 10, 1998Assignee: ENI Technologies, Inc.Inventor: Jeff C. Sellers
-
Patent number: 5651865Abstract: Pulses of positive voltage are applied to the target of a dc sputtering process to create a reverse bias. This charges insulating deposits on the target to the reverse bias level, so that when negative sputtering voltage is reapplied to the target, the deposits will be preferentially sputtered away. The reverse bias pulses are provided at a low duty cycle, i.e., with a pulse width of 0.25-3 microseconds at a pulse rate of about 40-100 KHz. This technique reduces sources for arcing during a reactive sputtering process.Type: GrantFiled: June 17, 1994Date of Patent: July 29, 1997Assignee: ENIInventor: Jeff C. Sellers
-
Patent number: 5627738Abstract: A soft start circuit for a high-power module permits trickle-charging of the capacitor bank prior to power switch actuation, and avoids large current surges or inrush at power up. Positive temperature coefficient thermistor devices, or PTCs are place in shunt across the switch elements or poles of the actuator or other power switch. In a power module that is powered by three-phase AC, the three power conductors are coupled through a three-pole contactor to AC inputs of a polyphase rectifier bridge, which has DC outputs coupled to the capacitor bank and to a load device, such as a high-power RF amplifier. The PTCs are connected, one per pole, in shunt across each pole of the contactor. Alternatively, metallized film capacitors can be employed in lieu of the PTCs.Type: GrantFiled: May 19, 1995Date of Patent: May 6, 1997Assignee: ENI, A Division of Astec America, Inc.Inventors: Vadim Lubomirsky, Jeff C. Sellers
-
Patent number: 5584974Abstract: A dc sputtering process applies a pulsating dc voltage in which each cycle includes a pulse portion of negative dc voltage of -300 to -700 volts alternating with a reverse bias (positive) pulse of about +50 to +300 volts. The reverse bias pulse portion will reduce or eliminate sources for arcing in most cases. To combat sticky or persistent arcing, the negative pulse portion is monitored. If, during a window portion of the negative pulse portion, the applied voltage drops into a range characteristic of arcing for two successive cycles, then the applied power is interrupted for a period, e.g., 200 microseconds, and reverse bias is applied. An overvoltage detection and clamping circuit monitors the applied voltage for extreme voltage excursions, and if an overvoltage threshold is exceeded for two successive cycles, the applied power is interrupted. The overvoltage detection and clamping circuit can comprise a string of zener diodes or equivalent voltage limiting devices connected to the applied voltage.Type: GrantFiled: October 20, 1995Date of Patent: December 17, 1996Assignee: ENIInventor: Jeff C. Sellers
-
Patent number: 5565737Abstract: An aliasing sampler probe for detecting plasma RF voltage and current employs a sampling signal with a sampling rate slower that the RF fundamental frequency selected to produce an aliasing waveform at an aliasing frequency that is several orders of magnitude below the RF fundamental frequency. In one embodiment, the RF power is applied at 13.56 MHz. and sampling pulses have a sampling rate of 2.732 MHz to produce replicas of the RF voltage and current waveforms at an aliasing frequency of about 100 KHz. The aliasing replicas preserve phase and harmonic information with an accuracy that is not available from other sampling techniques.Type: GrantFiled: June 7, 1995Date of Patent: October 15, 1996Assignee: ENI - a Division of Astec America, Inc.Inventor: Anthony R. A. Keane
-
Patent number: 5488331Abstract: A high-power radio-frequency amplifier acts on periodic pulses of RF energy. The bias is controlled for each of a bank of FETs or other amplifier devices that constitutes the main power stage. A sample of bias current is obtained during a blanking period on the front porch of the RF gating period. Quiescent drain current is measured, and stored on a sample/hold circuit. A digital signal processor provides bias values that are sent via a D/A converter to biasing circuits that add the bias levels to the input RF signal. If the bias current is above or below a desired level, the stored bias level is decreased or incremented respectively. A timing control circuit gates the sample/hold circuit and switches in advance of the biasing circuits. The timing control circuit also creates a blanking signal to apply to an attenuator to produce a null region during the first 100 microseconds of the gating signal.Type: GrantFiled: April 7, 1995Date of Patent: January 30, 1996Assignee: ENI, A Div. of Astec America, Inc.Inventors: Anthony R. A. Keane, Bart C. Vandebroek
-
Patent number: 5477188Abstract: A linear RF power amplifier employs push-pull pairs of high voltage mosfets. A minimum of transformers is employed, with an impedance matching transformer feeding an input balun supplying the input signal in push-pull to the gates of the mosfets. The drains are coupled to balanced legs of an output balun, followed by an output impedance matching transformer. Thermal sensors are employed for control of gate bias and also for control of drain voltage. The temperature sensors are mounted in the air inlet path and on the spreader plate of the heat sink. An aluminum or fiberglass strap is used to press the transistors against the spreader plate thereby ensuring good thermal contact with the transistor dies.Type: GrantFiled: July 14, 1994Date of Patent: December 19, 1995Assignee: ENIInventors: Yogendra K. Chawla, Leonid Reyzelman
-
Patent number: 5451907Abstract: A high-power radio-frequency amplifier act on periodic pulses of RF energy. The bias is controlled for each of a bank of FETs or other amplifier devices that constitutes the main power stage. A sample of bias current is obtained during a blanking period on the front porch of the RF gating period. Quiescent drain current is measured, and stored on a sample/hold circuit. A digital signal processor provides bias values that are sent via a D/A converter to biasing circuits that add the bias levels to the input RF signal. If the bias current is above or below a desired level, the stored bias level is decreased or incremented respectively. A timing control circuit gates the sample/hold circuit and switches in advance of the biasing circuits. The timing control circuit also creates a blanking signal to apply to an attenuator to produce a null region during the first 100 microseconds of the gating signal.Type: GrantFiled: May 16, 1994Date of Patent: September 19, 1995Assignee: ENI, Div. of Astec America, Inc.Inventors: Anthony R. A. Keane, Bart C. Vandebroek
-
Patent number: 5366991Abstract: 5-pyrazolecarboxylic acid amide-based insecticide and acaricide compounds of general formula (I): ##STR1## in which: R.sub.1 represents a hydrogen atom, a linear or branched C.sub.1 -C.sub.4 alkyl group or a benzyl group;R.sub.2 represents a hydrogen atom or a linear or branched C.sub.1 -C.sub.4 alkyl group;R.sub.x represents a hydrogen atom, a halogen atom such as chlorine, fluorine or bromine, or a linear or branched C.sub.1 -C.sub.4 alkyl or haloalkyl group; or R.sub.2 and R.sub.x together represent an RHC--(CH.sub.2).sub.n --CH.sub.2 group in which R represents a hydrogen atom or a C.sub.1 -C.sub.3 alkyl group and n is a whole number between 1 and 2;R.sub.3, R.sub.4, R.sub.5 represent, each independently, a hydrogen atom or linear or branched C.sub.1 -C.sub.4 alkyl group;X.sub.1, X.sub.2, X.sub.3 and X.sub.4 represent, each independently, a hydrogen atom or a halogen atom such as chlorine, fluorine or bromine;R.sub.y represents a linear or branched C.sub.3 -C.sub.Type: GrantFiled: September 27, 1993Date of Patent: November 22, 1994Assignee: Eni Chem Synthesis S.p.A.Inventors: Franco Bettarini, Luigi Capuzzi, Piero La Porta, Sergio Massimini, Franca Reggiori, Giovanni Meazza
-
Patent number: 5357002Abstract: Water insoluble polymers containing hydrophilic pendant moieties ending with a chelating group are disclosed. The polymers are useful in the purification of water polluted by heavy metals such as mercury and lead. The polymers have the general formula P--(--(--O--R).sub.n --(NH--Q).sub.p --F).sub.m where P is a polymeric matrix capable of reacting with a polyalkylene glycol or an alkylene oxide having such a structure and molecular weight as to be insoluble in water; R is either --CH.sub.2 CH.sub.2 -- or mixtures of --CH.sub.2 CH.sub.2 -- and --CH.sub.2 CH(CH.sub.3)--, with the molar ratio of both units in the mixture being at least 3:1; n is 3 to 50; m is a numeral such that the % by weight of all of the --(--(--O--R--).sub.n (NH--Q).sub.p --F hydrophilic chains is higher than 1% by weight of the total weight of (I); Q is a C.sub.2 -C.sub.Type: GrantFiled: December 18, 1992Date of Patent: October 18, 1994Assignee: Eni Chem Synthesis S.p.A.Inventors: Alessandro Lezzi, Arnaldo Roggero, Sandra Cobianco
-
Patent number: 5354454Abstract: A continuous process for deasphalting and demetallating a residue from crude oil distillation, by means of dimethyl carbonate as extraction solvent, comprises:mixing a residue from crude oil distillation with a recycled liquid stream containing oil and dimethyl carbonate, in order to produce a homogeneous solution;cooling said homogeneous solution and separating a refined light, liquid, phase; an extracted middle phase; and a heavy phase containing asphaltenes;recovering a primary, deasphalted/demetallated oil from said light phase;partially recycling said middle phase to the mixing step, and recovering a secondary deasphalted oil from the residual fraction;recovering asphaltenes from said heavy phase.Type: GrantFiled: April 19, 1993Date of Patent: October 11, 1994Assignee: Eni Chem Synthesis S.p.A.Inventors: Cesar Savastano, Roberto Cimino, Salvatore Meli
-
Patent number: 5326818Abstract: Polymeric stabilizers with a polysiloxanic structure contain sterically hindered phenol groups and reactive groups capable of binding themselves to the polymeric structure to be stabilized. These polymeric stabilizers are particularly suitable for applications which require the non-extractability of additives due to solvents, fats or soaps.Type: GrantFiled: December 2, 1993Date of Patent: July 5, 1994Assignee: Eni Chem Synthesis S.p.A.Inventors: Luciano Pallini, Daniele Fabbri, Rossella Farris, Carlo Neri
-
Patent number: 5323329Abstract: An RF generator has an analog feedback circuit in combination with a digital levelling assist circuit to compensate for non-linearities in the power metering circuit that measures the RF output energy. The digital leveling assist circuit has a digitizer with inputs coupled to receive the measured power voltage supplied from the power metering circuit and a power demand voltage. The digitizer has outputs that provide digital representations of the measured power voltage and the power demand voltage to a digital control element that derives a digital correction factor based on these digital representations. A d/a converter coupled to the digital control element provides a correction voltage corresponding to this digital correction factor, and this is furnished to a summing circuit that combines the correction voltage with the power demand voltage and with a control voltage that is supplied by the analog feedback circuit.Type: GrantFiled: December 23, 1991Date of Patent: June 21, 1994Assignee: ENI, Div. of Astec America, Inc.Inventor: Anthony R. A. Keane
-
Patent number: 5291063Abstract: A high-power RF feedback resistor assembly includes a flat film resistor or other flat device mounted in thermal communication onto a bushing which is, in turn, mounted directly onto a cooling flange of an associated power transistor. A bushing has a vertical bolt hole through it to receive a threaded screw. The bushing can have a cutout beneath the flat vertical surface on which the resistor is mounted to provide clearance for a printed circuit board.Type: GrantFiled: December 23, 1991Date of Patent: March 1, 1994Assignee: ENI Div. of Astec America, Inc.Inventor: Gary C. Adishian
-
Patent number: 5189601Abstract: A dc-dc converter employs both half-bridge topology and current-mode switching control. The controller operates by sensing the current that flows through the transformer that is interposed between the node of two series switches and the node between the two split capacitors. The controller develops gating signals to close and open the switches based on the rise of current to a predetermined command level. A gate signal for the second switch, which is developed between actuations of the first switch, has its pulse width made equal to the period that the first switch was closed. This maintains a balanced voltage-time product, so that the series or split capacitors remain in balance. The controller can include a sample gating circuit with a comparator that receives the current sample signal and the command level. The track side signal which develops the gating pulse for the other switch can be developed with analog circuitry, i.e. by charging a capacitor, or else digitally, i.e. by clock pulse counting.Type: GrantFiled: November 18, 1991Date of Patent: February 23, 1993Assignee: ENI Div. of Astec America, Inc.Inventor: Jeff C. Sellers