Patents Assigned to Ensiltech Corporation
  • Publication number: 20140050847
    Abstract: Provided are a deposition method of patterning a thin film on a substrate using momentary Joule heating in a vacuum environment, and a method thereof. The deposition device forms a deposition target layer on one surface of a source substrate as a pattern to be deposited. A deposition target layer forming unit forms a deposition target layer on the one surface of the source substrate to cover the conductive layer. A chamber in a vacuum state receives the source substrate on which the conductive layer and the deposition target layer are formed and the target substrate. A target substrate is disposed in the chamber to face the source substrate. A power supply applies power to the conductive layer to heat-generate the conductive layer. A configuration of the deposition device is very simple, and it is easy to uniformly form a deposition thickness.
    Type: Application
    Filed: August 20, 2012
    Publication date: February 20, 2014
    Applicant: EnSilTech Corporation
    Inventors: Jae-Sang RO, Won-Eui Hong, Seog-Young Lee, Ingoo Jang
  • Patent number: 8603869
    Abstract: Provided are thin film transistor, a method of fabricating the same, a flat panel display device including the same, and a method of fabricating the flat panel display device, that are capable of applying an electric field to a gate line to form a channel region of a semiconductor layer of a thin film transistor using a polysilicon layer crystallized by a high temperature heat generated by Joule heating of a conductive layer. As a result, a process can be simplified using a gate line included in the thin film transistor as the conductive layer, and the channel region of the semiconductor layer can be formed of polysilicon having a uniform degree of crystallinity. The thin film transistor includes a straight gate line disposed in one direction, a semiconductor layer crossing the gate line, and source and drain electrodes connected to source and drain regions of the semiconductor layer.
    Type: Grant
    Filed: November 20, 2008
    Date of Patent: December 10, 2013
    Assignee: Ensiltech Corporation
    Inventors: Jae-Sang Ro, Won-Eui Hong
  • Publication number: 20130267055
    Abstract: Provided are a deposition substrate of a deposition apparatus, a method of forming a layer using the same, and a method of manufacturing an organic light emitting diode (OLED) display device. The method of forming a layer using the deposition substrate includes preparing a substrate, forming a heating conductive layer for Joule heating on the substrate, forming a first insulating layer on the heating conductive layer for Joule heating and including a groove or hole, forming a deposition material layer on a top surface of the first insulating layer having the groove or hole, and applying an electric field to the heating conductive layer for Joule heating to perform Joule-heating on the deposition material layer. Thus, the method is suitable for manufacturing a large-sized device.
    Type: Application
    Filed: July 7, 2010
    Publication date: October 10, 2013
    Applicant: ENSILTECH CORPORATION
    Inventors: Jae-Sang Ro, Won-Eui Hong
  • Publication number: 20130089954
    Abstract: There is provided a method of fabricating an electronic device having a flexible device, which is fabricated using a support substrate by Joule-heating induced film separation (JIFS). A method of fabricating an electronic device having a flexible device includes providing a support substrate, coating a conductive layer on one surface of the support substrate, forming a plastic substrate on the other surface of the support substrate, forming one or more thin-film transistors (TFTs) on the plastic substrate, forming an electronic device electrically connected to any one of the TFTs, and separating the plastic substrate from the conductive layer by generating Joule-heating through application of an electric field to the conductive layer. Accordingly, the flexible device can be separated from the support substrate without deformation of the support substrate and degradation of the electronic device.
    Type: Application
    Filed: October 6, 2012
    Publication date: April 11, 2013
    Applicant: EnSilTech Corporation
    Inventor: EnSilTech Corporation
  • Patent number: 8400057
    Abstract: An organic electroluminescence apparatus comprises: a substrate having a pixel region and sealing regions; an organic electroluminescence device located in the pixel region of the substrate; and a sealing substrate having a pixel region and sealing regions corresponding to the pixel region and the sealing regions of the substrate. The sealing regions of the sealing substrate comprise conductive layers continuously connected to each other. In a method of manufacturing organic electroluminescence apparatus by sealing the substrate and the sealing substrate using a glass frit, manufacturing costs and process time can be greatly reduced.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: March 19, 2013
    Assignees: Samsung Display Co., Ltd., EnsilTech Corporation
    Inventors: Oh-Seob Kwon, Dong-Seop Park, Jung-Jun Im, Jae-Sang Ro, Won-Eui Hong, Seog-Young Lee
  • Publication number: 20130047920
    Abstract: There are provided a deposition device for forming an organic layer using Joule heating and a device for fabricating an electroluminescent display device using the deposition device that includes a cleansing device, an organic matter coating device, an electric field applying device and a loadlock chamber. The cleansing device cleanses a donor substrate. The organic matter coating device coats an organic matter on the donor substrate. The electric field applying device allows the organic matter to be transferred onto an element substrate. Here, the organic matter is heated by the Joule-heating generated by applying an electric field to the donor substrate having the organic matter formed thereon. The loadlock chamber loads or carries out the donor substrate into/from the electric field applying device. Accordingly, the present invention is advantageous in fabricating a large-scale element, and it is possible to increase a processing speed and to reduce device cost.
    Type: Application
    Filed: August 22, 2012
    Publication date: February 28, 2013
    Applicant: EnSilTech Corporation
    Inventors: Jae-Sang RO, Won-Eui Hong
  • Publication number: 20120164819
    Abstract: An apparatus and method for fabricating a polycrystalline silicon (poly-Si) thin film are provided. The apparatus includes a chamber, a substrate stage installed at a lower portion in the chamber and on which a substrate including a conductive layer is located, a power application unit installed at an upper portion in the chamber and including an electrode terminal applying power to the conductive layer, and a conductive pad interposed between the electrode terminal and the conductive layer. Thus, it is possible to form a uniform electric field on the conductive layer, and to form a good quality of poly-Si thin film.
    Type: Application
    Filed: December 27, 2010
    Publication date: June 28, 2012
    Applicant: ENSILTECH CORPORATION
    Inventors: Jae-Sang RO, Won-Eui HONG
  • Patent number: 8128714
    Abstract: Provided is an apparatus for manufacturing a polysilicon thin film by depositing an amorphous silicon thin film and an upper silicon dioxide substrate on a lower silicon dioxide substrate, forming a conductive thin film on the upper silicon dioxide substrate, and applying an electric field and performing Joule heating to crystallize the amorphous silicon thin film, the apparatus comprising power terminals for elastically contacting both upper ends of the conductive thin film and supplying power to the conductive thin film, and support members for elastically supporting the substrate such that the power terminals closely contact both upper ends of the conductive thin film to form a uniform electric field at the conductive thin film.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: March 6, 2012
    Assignee: Ensiltech Corporation
    Inventors: Jae-Sang Ro, Won-Eui Hong
  • Patent number: 8124530
    Abstract: Disclosed herein is a rapid annealing method in a mixed structure composed of a heat treatment-requiring material, dielectric layer and conductive layer, comprising that during rapid annealing on a predetermined part of the heat treatment-requiring material, by instantaneously generated intense heat due to Joule heating by application of an electric field to the conductive layer, the potential difference between the heat treatment-requiring material and the conductive layer is set lower than the dielectric break-down voltage of the dielectric layer, thereby preventing generation of arc by dielectric breakdown of the dielectric layer during the annealing.
    Type: Grant
    Filed: January 10, 2007
    Date of Patent: February 28, 2012
    Assignee: Ensiltech Corporation
    Inventors: Jae-Sang Ro, Won-Eui Hong
  • Publication number: 20110121308
    Abstract: Provided are a thin film transistor including a polycrystalline silicon layer having improved crystallinity by applying Joule heat to form stress gradient in a glass substrate that is disposed under an amorphous silicon layer from a surface to a predetermined depth of the glass substrate, thereby crystallizing the amorphous silicon layer into a polycrystalline silicon layer, and a method of fabricating the same. The film transistor includes a glass substrate having stress gradient from an upper surface to a predetermined depth, a semiconductor layer disposed on the glass substrate, and formed of a polycrystalline silicon layer crystallized by Joule heating, a gate insulating layer disposed on the semiconductor layer, a gate electrode disposed on the gate insulating layer, an interlayer insulating layer disposed on the gate electrode, and source and drain electrodes disposed on the interlayer insulating layer, and electrically connected to source and drain regions of the semiconductor layer.
    Type: Application
    Filed: July 8, 2009
    Publication date: May 26, 2011
    Applicant: ENSILTECH CORPORATION
    Inventors: Jae-Sang Ro, Won-Eui Hong
  • Publication number: 20110115370
    Abstract: An organic electroluminescence apparatus comprises: a substrate having a pixel region and sealing regions; an organic electroluminescence device located in the pixel region of the substrate; and a sealing substrate having a pixel region and sealing regions corresponding to the pixel region and the sealing regions of the substrate. The sealing regions of the sealing substrate comprise conductive layers continuously connected to each other. In a method of manufacturing organic electroluminescence apparatus by sealing the substrate and the sealing substrate using a glass frit, manufacturing costs and process time can be greatly reduced.
    Type: Application
    Filed: November 18, 2010
    Publication date: May 19, 2011
    Applicants: SAMSUNG MOBILE DISPLAY CO., LTD., ENSILTECH CORPORATION
    Inventors: Oh-Seob Kwon, Dong-Seop Park, Jung-Jun Im, Jae-Sang Ro, Won-Eui Hong, Seog-Young Lee
  • Publication number: 20100313397
    Abstract: Provided is an apparatus for manufacturing a polysilicon thin film by depositing an amorphous silicon thin film and an upper silicon dioxide substrate on a lower silicon dioxide substrate, forming a conductive thin film on the upper silicon dioxide substrate, and applying an electric field and performing Joule heating to crystallize the amorphous silicon thin film, the apparatus comprising power terminals for elastically contacting both upper ends of the conductive thin film and supplying power to the conductive thin film, and support members for elastically supporting the substrate such that the power terminals closely contact both upper ends of the conductive thin film to form a uniform electric field at the conductive thin film.
    Type: Application
    Filed: January 30, 2009
    Publication date: December 16, 2010
    Applicant: ENSILTECH CORPORATION
    Inventors: Jae-Sang Ro, Won-Eui Hong
  • Publication number: 20100270558
    Abstract: Provided are a method of fabricating a polycrystalline silicon thin film using high temperature heat generated by Joule heating induced by application of an electrical field to a conductive layer, which can ensure process stability at high temperature and thus processing time can be reduced and a polycrystalline silicon thin film having excellent crystallinity can be obtained, a polycrystalline thin film using the method and a thin film transistor including the polycrystalline thin film.
    Type: Application
    Filed: November 21, 2008
    Publication date: October 28, 2010
    Applicant: ENSILTECH CORPORATION
    Inventors: Jae-Sang Ro, Won-Eui Hong
  • Publication number: 20100244038
    Abstract: Provided are thin film transistor, a method of fabricating the same, a flat panel display device including the same, and a method of fabricating the flat panel display device, that are capable of applying an electric field to a gate line to form a channel region of a semiconductor layer of a thin film transistor using a polysilicon layer crystallized by a high temperature heat generated by Joule heating of a conductive layer. As a result, a process can be simplified using a gate line included in the thin film transistor as the conductive layer, and the channel region of the semiconductor layer can be formed of polysilicon having a uniform degree of crystallinity. The thin film transistor includes a straight gate line disposed in one direction, a semiconductor layer crossing the gate line, and source and drain electrodes connected to source and drain regions of the semiconductor layer.
    Type: Application
    Filed: November 20, 2008
    Publication date: September 30, 2010
    Applicant: ENSILTECH CORPORATION
    Inventors: Jae-Sang Ro, Won-Eui Hong
  • Publication number: 20100233858
    Abstract: Disclosed herein is a rapid annealing method in a mixed structure composed of a heat treatment-requiring material, dielectric layer and conductive layer, comprising that during rapid annealing on a predetermined part of the heat treatment-requiring material, by instantaneously generated intense heat due to Joule heating by application of an electric field to the conductive layer, the potential difference between the heat treatment-requiring material and the conductive layer is set lower than the dielectric break-down voltage of the dielectric layer, thereby preventing generation of arc by dielectric breakdown of the dielectric layer during the annealing.
    Type: Application
    Filed: January 10, 2007
    Publication date: September 16, 2010
    Applicants: ENSILTECH CORPORATION
    Inventors: Jae-Sang Ro, Won-Eui Hong