Abstract: The present disclosure provides a clock generator circuit comprising a master clock generator unit configured to generate a master clock signal, and a plurality of slave phase locked loop units. Each of the plurality of slave phase looked loop units is configured to receive the master clock signal as an input reference signal and a corresponding source clock signal. The slave phase locked loop unit may comprise an inner loop and an outer loop. The inner loop may comprise a frequency synthesizer locked on a master clock signal received from a master clock generator unit, while the outer loop may comprise a binary phase detector, an output of which goes to a loop filter with proportional and integral action, controlling the inner loop frequency value via a sigma delta input.

Abstract: A receiving unit using a voltage-controlled oscillator is allowed to compensate for the frequency characteristics of the voltage-controlled oscillator resulting from temperature change, without adding a capacitive element for temperature compensation. A receiving unit and an optical line terminal include a clock and data recovery circuit that extracts a clock signal and a data signal from a received signal, and have: a calibrator that calibrates an oscillation frequency of a voltage-controlled oscillator included in the clock and data recovery circuit; and a managing unit having a function of managing a schedule for receiving signals, the managing unit selecting a time where a duration of a certain state meets a time required for calibration by the calibrator to thereby output a reset signal (calibration instruction signal) to the calibrator, the state having no received signal (upstream signal) from which a clock signal and a data signal are to be extracted.

Abstract: The present disclosure provides a clock data recovery circuit that includes a phase locked loop unit, a delay locked loop unit and digital clock data recovery unit. The phase locked loop unit generates a clock signal based on a reference signal. The delay locked loop unit receives the clock signal from the phase locked loop, divides the clock signal into a plurality of clock signals and outputs the clock signals. The digital clock data recovery unit receives an input current signal, estimates a frequency of the input current signal, outputs a reference signal having the frequency, which can be transmitted to the phase locked loop unit, receives the clock signals from the delay locked loop, aligns a phase of the input current signal based on the clock signals and outputs an aligned current signal.

Abstract: The present disclosure provides a clock generator circuit comprising a master clock generator unit configured to generate a master clock signal, and a plurality of slave phase locked loop units. Each of the plurality of slave phase looked loop units is configured to receive the master clock signal as an input reference signal and a corresponding source clock signal. The slave phase locked loop unit may comprise an inner loop and an outer loop. The inner loop may comprise a frequency synthesizer locked on a master clock signal received from a master clock generator unit, while the outer loop may comprise a binary phase detector, an output of which goes to a loop filter with proportional and integral action, controlling the inner loop frequency value via a sigma delta input.

Abstract: Embodiments of a device include a receive multi-rate CDR unit communicatively coupled to a processor, the receive multi-rate CDR configured to receive signals from a cable and perform clock and data recovery on signals and a transmitter multi-rate CDR unit communicatively coupled to a processor, the transmit multi-rate CDR configured to send signals to the cable after performing clock and data recovery on the signals. Embodiments of the cable include a receiver equalizer configured to receive signals from a wire and a transmitter equalizer configured to receive signals from a connector of the cable and configured to transmit an equalized signal to the wire.