Patents Assigned to Entasys Designs, Inc.
  • Patent number: 8327306
    Abstract: The present invention relates to a method for optimizing power/ground pads in a power/ground distribution network. A power/ground distribution network is created for each of multiple voltage domains and a load current source of each node of the power/ground distribution network is modeled in consideration of the actual shapes and areas of functional blocks. A local optimization method is developed to solve problems generated when a conventional optimization method is applied to optimization of power/ground pads in a bump shape used for a flip chip, and a combination of global optimization and local optimization is applied to layouts using bump bonding, which is discriminated from the conventional optimization method restrictively applicable to layouts using wire bonding.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: December 4, 2012
    Assignee: Entasys Designs, Inc.
    Inventors: Sung Hwan Oh, Dong Jin Shin
  • Publication number: 20080098340
    Abstract: The present invention relates to a method for designing initial placement of functional blocks and designing power distribution network of a semiconductor integrated circuit in the next stage of architecture level design of integrated circuit, which estimates the area and the quantity of power consumption of functional blocks and integrated circuit using design specifications of the functional blocks constructing the integrated circuit, that is, interconnection between functional blocks and an estimated size of the functional blocks which is determined in an architecture level design process. The present invention enables initial functional block placement in consideration of power consumption of the functional blocks and analyze reliability of power distribution network even prior to detailed circuit design.
    Type: Application
    Filed: November 25, 2005
    Publication date: April 24, 2008
    Applicant: Entasys Design, Inc.
    Inventor: Sung Hwan Oh