Abstract: A circuit ? is coupled to an individual node Nin, in a circuit for which repeated logical values of that individual node can be identified as having a set of flip-flops Fj dependent thereon, with the effect that if the individual node Nin remains unchanged for one or more clock cycles, the set of dependent flip-flops Fj can be disabled for the second and succeeding clock cycles. The circuit ? conditionally generates a clock-enabling signal Nout in response thereto. One such circuit ? conditionally includes a logical controller, whose output is coupled using a fan-out node to both an input to a state machine and a fan-in logic circuit (such as an AND gate). The flip-flop is clocked normally; its output is coupled to that same fan-in logic circuit, whose output Nout is coupled to the set of dependent flip-flops Fj.