Patents Assigned to Eon Silicon Solution Inc.
  • Patent number: 8982641
    Abstract: A memory erasing method and a driving circuit thereof are introduced, when cells are selected to be erased, the method includes setting gates of cells which are not selected to be erased and are located at a selected block, drains of all the cells in a selected bank, and the gate of the unselected cells to be floating; supplying a positive voltage to all the sources in a selected bank and their shared P well and N well; and supplying a negative voltage to the gates of the cells located in a selected block and selected to be erased. Accordingly, a positive coupling voltage from P wells is received whenever gates are floating, so as to inhibit erasure of unselected blocks and thereby streamline decoding, thus making it easy to attain further expansion of blocks or banks with a small layout area and partition of sectors in the blocks.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: March 17, 2015
    Assignee: EON Silicon Solution Inc.
    Inventors: Hsiao-Hua Lu, Chih-Ming Kuo, Yu-Chun Wang
  • Patent number: 8923083
    Abstract: A method of identifying a damaged bitline address in a non-volatile memory device is introduced. The non-volatile memory device includes a memory cell array and a plurality of bit lines crossing the memory cell array. Each bit line has a first end and a second end. The bit lines are divided into a first group and a second group. The method includes applying a source voltage (charging) or ground voltage (discharging) to a specific group of bit lines, testing the bit lines in two testing stages (open-circuit testing and short-circuit testing) by the principle that no damaged bit line can be charged or discharged, and acquiring an address data of a damaged bit line according to a status data stored in a page buffering circuit and related to whether a bit line is damaged, thereby dispensing with a calculation process for estimating the address of the damaged bit line.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: December 30, 2014
    Assignee: Eon Silicon Solution Inc.
    Inventors: Takao Akaogi, Tony Chan
  • Patent number: 8730739
    Abstract: A semiconductor device and a method for accelerating erase verification process thereof are introduced, in which a correction unit of erase verification is connected between broken bit lines of the semiconductor device and a page buffer. Grounding switches in the correction unit of erase verification are allowed to connect the broken bit lines to ground during an erase verification process by means of a specific circuit arrangement with respect to the broken lines. Thereby, the earth voltage is received, and further, that the broken bit lines pass the erase verification is identified by the page buffer, further saving time consumed in repeated verifications in the conventional technology significantly.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: May 20, 2014
    Assignee: Eon Silicon Solution Inc.
    Inventor: Tony Chan
  • Patent number: 8654591
    Abstract: In a local word line driver of an NOR flash memory and its flash memory array device, the local word line driver is provided for driving a local word line in a sector of a memory array, and the local word line driver has two transistors including a first transistor and a second transistors, and the first and second transistors are NMOS transistors, and thus achieving the effects of reducing the area occupied by circuits on the local word line driver and the die size, and saving the area for the use by memory units.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: February 18, 2014
    Assignee: Eon Silicon Solution Inc.
    Inventor: Takao Akaogi
  • Patent number: 8633744
    Abstract: A power reset circuit with zero standby current consumption includes a power storage unit, first, second, and third voltage detection units, a switching unit, and a power reset unit. The power storage unit stores electric power by a supply voltage source. The first, second, and third voltage detection units are connected to the supply voltage source to start a switching circuit of the first, second, and third voltage detection units in accordance with a change in a normal supply stage, a shutdown stage, and a voltage ramp-up stage of the supply voltage source, control a voltage level of the power reset unit, and thereby generate the power reset signal. Accordingly, the power reset circuit does not consume current in a standby state (the normal supply stage of the supply voltage source) and thus is characterized by zero current consumption.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: January 21, 2014
    Assignee: Eon Silicon Solutions, Inc.
    Inventors: Hsiao-Hua Lu, Chih-Ming Kuo, Yu-Chun Wang
  • Patent number: 8537629
    Abstract: A method of testing bitlines in a non-volatile memory device is introduced. The non-volatile memory device includes a memory cell array and a plurality of bitlines crossing the memory cell array. Each of the bitlines has a first end and a second end. The bitlines are divided into a first group and a second group. The testing method includes applying a supply voltage (for charging) or a ground voltage (for discharging) to a specific group of bitlines. The bitlines are tested in two testing stages, namely an open-circuit bitline test and a short-circuit bitline test, based on the feature that a defective bitline cannot be charged or discharged. The open-circuit bitline test and the short-circuit bitline test are quick and dispense with a lengthy programmed/erasing process.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: September 17, 2013
    Assignee: Eon Silicon Solution Inc.
    Inventor: Tony Chan
  • Patent number: 8476156
    Abstract: In a manufacturing method of a flash memory structure with a stress area, a better stress effect can be achieved by controlling the manufacturing process of a tunneling oxide layer formed in a gate structure and contacted with a silicon substrate, so that an L-shaped spacer (or a first stress area) and a contact etch stop layer (or a second stress area) of each L-shaped spacer are formed between two gate structures and aligned towards each other to enhance the carrier mobility of the gate structure, so as to achieve the effects of improving a read current, obtaining the required read current by using a lower read voltage, reducing the possibility of having a stress-induced leakage current, and enhancing the data preservation of the flash memory.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: July 2, 2013
    Assignee: Eon Silicon Solution Inc.
    Inventors: Yider Wu, Hung-Wei Chen
  • Patent number: 8325518
    Abstract: A multi-level cell NOR flash memory device includes a plurality of gate lines, a plurality of source regions, a plurality of drain regions, a plurality of source lines, a plurality of bitlines, and a plurality of power lines. The bitlines each have a specific sheet resistance. A specific number of the bitlines are disposed between two adjacent ones of the power lines. Accordingly, the multi-level cell NOR flash memory device is of a high transconductance and uniformity and thereby features an enhanced conforming rate.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: December 4, 2012
    Assignee: Eon Silicon Solution Inc.
    Inventors: Sheng-Da Liu, Yider Wu
  • Patent number: 8158519
    Abstract: In a method of manufacturing a non-volatile memory cell, a self-aligned metal silicide is used in place of a conventional tungsten metal layer to form a polysilicon gate, and the self-aligned metal silicide is used as a connection layer on the polysilicon gate. By using the self-aligned metal silicide to form the polysilicon gate, the use of masks in the etching process may be saved to thereby enable simplified manufacturing process and accordingly, reduced manufacturing cost. Meanwhile, the problem of resistance shift caused by an oxidized tungsten metal layer can be avoided.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: April 17, 2012
    Assignee: Eon Silicon Solution Inc.
    Inventors: Yi-Hsiu Chen, Yung-Chung Lee, Yider Wu
  • Patent number: 8017488
    Abstract: A manufacturing method of a NOR flash memory with phosphorous and arsenic ion implantations mainly implants both phosphorous and arsenic ions on a drain area of a transistor memory unit, and controls specific energy and dosage for the implantation to reduce the defects of a memory device and improve the yield rate of the NOR flash memory.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: September 13, 2011
    Assignee: EON Silicon Solutions Inc.
    Inventors: Sheng-Da Liu, Yider Wu
  • Patent number: 8012825
    Abstract: In a method of manufacturing a double-implant NOR flash memory structure, a phosphorus ion implantation process is performed, so that a P-doped drain region is formed in a semiconductor substrate between two gate structures to overlap with a highly-doped drain (HDD) region and a lightly-doped drain (LDD) region. Therefore, the electric connection at a junction between the HDD region and the LDD region is enhanced and the carrier mobility in the memory is not lowered while the problems of short channel effect and punch-through of LDD region are solved.
    Type: Grant
    Filed: January 8, 2009
    Date of Patent: September 6, 2011
    Assignee: EON Silicon Solutions Inc.
    Inventors: Yider Wu, Yung-Chung Lee, Yi-Hsiu Chen
  • Patent number: 8008692
    Abstract: A semiconductor memory structure with stress regions includes a substrate defining a first and a second device zone; a first and a second stress region formed in each of the first and second device zone to yield stress different in level; a barrier plug separating the two device zones from each other; and a plurality of oxide spacers being located between the first stress regions and the barrier plug while in direct contact with the first stress regions. Due to the stress yielded at the stress regions, increased carrier mobility and accordingly, increased reading current can be obtained, and only a relatively lower reading voltage is needed to obtain an initially required reading current. As a result, the probability of stress-induced leakage current is reduced to enhance the data retention ability.
    Type: Grant
    Filed: September 18, 2008
    Date of Patent: August 30, 2011
    Assignee: EON Silicon Solution Inc.
    Inventors: Hung-Wei Chen, Yider Wu
  • Patent number: 7939423
    Abstract: A non-volatile semiconductor manufacturing method comprises the steps of making element isolation/insulation films that partitions element-forming regions in a semiconductor substrate; stacking a floating gate on the semiconductor substrate via a first gate insulating film; stacking a second gate insulating film formed on the floating gate, and stacking a control gate formed on the floating gate via the second gate insulating film, and self-aligning source and drain diffusion area with the control gate. In the process of stacking a floating gate by partially etching a field oxide film in a select gate area, followed by floating gate formed in a element-forming region and select gate region, and followed by a chemical mechanical polish(CMP) process, both floating gate and select gate is hereby formed simultaneously. Thereby, when memory cells are miniaturized, the invention allows the process to be simple and reduce the defect density.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: May 10, 2011
    Assignee: Eon Silicon Solution Inc.
    Inventor: Yider Wu
  • Publication number: 20110070705
    Abstract: A manufacturing method of a NOR flash memory with phosphorous and arsenic ion implantations mainly implants both phosphorous and arsenic ions on a drain area of a transistor memory unit, and controls specific energy and dosage for the implantation to reduce the defects of a memory device and improve the yield rate of the NOR flash memory.
    Type: Application
    Filed: September 18, 2009
    Publication date: March 24, 2011
    Applicant: Eon Silicon Solutions Inc.
    Inventors: SHENG-DA LIU, YIDER WU
  • Patent number: 7529132
    Abstract: A single-poly non-volatile memory includes a storing node, a control node and a floating gate. While a programming operation is executed, a bit line is provided with a low voltage and a control line is provided with a high voltage so that a coupling voltage occurs in the floating gate. The voltage difference between the floating gate and the storing node is able to send electrons into the floating gate, but the voltage difference between the floating gate and the control node is not enough to expel electrons from the floating gate. While an erasing operation is executed, a bit line is provided with a high voltage and a control line is provided with a low voltage so that a coupling voltage occurs on the floating gate. The voltage difference between the floating gate and the storing node is able to expel electrons from the floating gate, but the voltage difference between the floating gate and the control node is not enough to send electrons into the floating gate.
    Type: Grant
    Filed: June 13, 2007
    Date of Patent: May 5, 2009
    Assignee: Eon Silicon Solution Inc.
    Inventors: Chao Yang Chen, Yider Wu, Hsiao Hua Lu
  • Publication number: 20080079059
    Abstract: A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isolate stripe-shaped element-forming regions. Formed on the substrate area floating gate via a first gate insulating film and further a control gate via a second gate insulating film. Source and drain diffusion layers are formed in self-alignment with control gates. The second gate insulating film on the floating gate is divided and separated together with the floating gate by slits above the element isolation/insulation films into discrete portions of individual memory cells. The select gate is formed with a STI recess process in advance locally in the select area.
    Type: Application
    Filed: April 20, 2007
    Publication date: April 3, 2008
    Applicant: Eon Silicon Solution Inc.
    Inventor: Yider Wu