Abstract: A memory device is provided. The device comprises a substrate, a controller, at least a tap, a plurality of memory modules, and at least two resistors. The controller connects to the substrate. The tap, the memory modules, and the resistors are set on the substrate. The tap comprises an input terminal connecting to the controller; a first output terminal; and a second output terminal. After connecting to each other in series, the memory modules connect to the first output terminal and the second output terminal. Each of the resistors connects to one of the memory modules which connect to the first output terminal and the second output terminal. Thus, command signals, address signals, and timing signals are separately sent to the memory modules through the first output terminal and the second output terminal of the tap simultaneously to process instruction or read information by the controller.

Abstract: A memory layout is provided. The layout comprises a circuit board, a plurality of memories, a processing unit, and a reflection absorption unit. The circuit board has a first surface and a second surface. The first surface is set with a first wire unit and a second wire unit corresponding to each other. The memories are separately set on the first and second surfaces of the circuit board and connect to the first and second wire units. The processing unit connects to the first wire unit. The reflection absorption unit connects to the second wire unit. Thus, not only the capacity of the memories is increased, but also, during operating the memories, related reflection signals are absorbed by the reflection absorption unit for stably operating the memories with operation velocity enhanced as well.

Abstract: A memory comprising substrates is provided. Each substrate comprises a through-hole area at center; a first contact area at a side of the through-hole area; and a second contact area at another side of the through-hole area. The substrate uses its first or second contact area to mutually electrically connects to the first or second contact area of the another substrate through the through-hole area. After the pins of the memory having at least PAR pin included are electrically connects to the first and second contact areas of the substrate, all the substrates obtain mutual connections across layers through signal lines with the guidance of the through-hole areas. Thus, on fabricating the memory, reference layer is effectively prevented from breaks with good power distribution and sufficient wiring space achieved while good signal integrity is further maintained.

Abstract: A memory chip is disclosed. The memory comprises a substrate and a plurality of memory pads. The plurality of memory pads are disposed around the substrate so as to form a pattern, and the plurality of memory pads are configured in a mirror horizontal manner and with layout line connectivity, so as to simplify complexity of layout line. Mirror solder ball map of the instant disclosure increases design flexibility and convenience of integrating line characteristics of the end product's application, and is easy to achieve the design of doubling the memory capacity.

Abstract: A memory comprises a substrate and memory ball pads. The memory ball pads are disposed around the substrate so as to form a ring pattern which show a bilateral symmetry by reflection, wherein the memory ball pads of left-half part of the ring pattern are divided into a first main area, a second main area, a third main area and a fourth main area. The memory ball pads in the first main area are divided into a first sub-region, a second sub-region and a third sub-region, and a plurality of input/output data pins and electricity power pins are disposed in the first sub-region and the third sub-region, wherein the input/output data pins are not adjacent to each other and at least one power voltage pin and at least one ground voltage pin are disposed next to each of the input/output data pins.

Abstract: A series control circuit is disclosed. The series control circuit comprises a master driving control module and N driving control modules. The master driving control module receiving an alternative current voltage is used for transmits a command packet via a data line according to a firmware, wherein the command packet comprises an identification code and a work instruction. The driving control module receives the command packet and determines whether a local address code is equal to the identification code. If the local address code is equal to the identification code, the driving control module transmits a driving signal to a designated driving channel. If the local address code is not equal to the identification code, the driving control module transmits the command packet to next driving control module.

Abstract: A memory device is provided. The memory device is used for data transmission at around 1600 megahertz (MHz). A wire layout is used to sequentially cascade memory dices with greatly shortened distances between the wire layout and the memory dices. At the same time, distances between the wire layout and UA controllers are shortened as well for effectively simplifying the design of wires.

Abstract: A memory structure with reduced-reflection signals at least includes a processing unit; a lumped circuit unit, connected to the processing unit; a plurality of memories, connected to the lumped circuit unit; and a reflected signal absorption unit, disposed at one end of the lumped circuit unit. Thereby, with the cooperation of the processing unit with each memory for signal transmission, the reflected signal absorption unit can be used to absorb the reflected signals so as to reduce the number of reflected signals during signal transmission, achieving the effect of stable operation for the memories.

Abstract: A memory device is provided. The memory device is used for data transmission at around 1600 megahertz (MHz). A wire layout is used to sequentially cascade memory dices with greatly shortened distances between the wire layout and the memory dices. At the same time, distances between the wire layout and UA controllers are shortened as well for effectively simplifying the design of wires.

Abstract: A memory structure with reduced-reflection signals at least includes a processing unit; a lumped circuit unit, connected to the processing unit; a plurality of memories, connected to the lumped circuit unit; and a reflected signal absorption unit, disposed at one end of the lumped circuit unit. Thereby, with the cooperation of the processing unit with each memory for signal transmission, the reflected signal absorption unit can be used to absorb the reflected signals so as to reduce the number of reflected signals during signal transmission, achieving the effect of stable operation for the memories.