Abstract: A biochip includes a substrate, an insulating layer, a semiconductor layer, a dielectric layer, a metal layer, and a protective layer. The semiconductor layer is disposed on the insulating layer and has a reaction region. The dielectric layer is disposed on the semiconductor layer and has a first opening. The metal layer is disposed on the dielectric layer and includes a source, a drain, and a wall structure. The wall structure surrounds the first opening, the source, and the drain. The protective layer is disposed on the metal layer and has a flat part, a protruding part, a second opening, and a third opening. The flat part surrounds and defines the second opening. The protruding part is disposed corresponding to the wall structure, and the protruding part surrounds and defines the third opening. The second opening connects the third opening and the first opening to expose the reaction region.

Abstract: A structure for suppressing current leakage and a semiconductor device including the same are provided. The structure for suppressing current leakage includes a substrate of a first conductivity type, a well region of the first conductivity type, an isolation structure and a PN junction diode. The well region is disposed in the substrate. The isolation structure is disposed on the well region. The PN junction diode is disposed on the isolation structure and configured to suppress current leakage of the semiconductor device.

Abstract: An ESD protection structure includes a first conductive type substrate; first and second well regions of a first conductive type; a third well region of a second conductive type located between the first and second well regions; a first doped region of the first conductive type and a second doped region of the second conductive type disposed in the first well region; a third doped region of the first conductive type and a fourth doped region of the second conductive type disposed in the second well region; and fifth and sixth doped regions disposed at an interface of the first and third well regions or an interface of the second and third well regions. The fifth doped region of the first conductive type is located in the first or second well region, and the sixth doped region of the second conductive type is located in the third well region.

Abstract: A power LDMOS device including a substrate, source and drain regions, gates and trench insulating structures is provided. The substrate has a finger tip area, a finger body area and a palm area. The source regions are in the substrate in the finger body area and further extend to the finger tip area. The neighboring source regions in the finger tip area are connected. The outmost two source regions further extend to the palm area and are connected. The drain regions are in the substrate in the finger body area and further extend to the palm area. The neighboring drain regions in the palm area are connected. The source and drain regions are disposed alternately. A gate is disposed between the neighboring source and drain regions. The trench insulating structures are in the substrate in the palm area and respectively surround ends of the drain regions.

Abstract: A reduced surface field (RESURF) structure and a lateral diffused metal oxide semiconductor (LDMOS) device including the same are provided. The RESURF structure includes a substrate of a first conductivity type, a deep well region of a second conductivity type, an isolation structure, at least one trench insulating structure, and at least one doped region of the first conductivity type. The deep well region is disposed in the substrate. The isolation structure is disposed on the substrate. The trench insulating structure is disposed in the deep well region below the isolation structure. The doped region is disposed in the deep well region and surrounds a sidewall and a bottom of the trench insulating structure.

Abstract: A submount for a light emitting diode and a method for fabricating the same are provided. The method includes the following steps: (a) providing a silicon substrate; (b) forming a mask layer on the silicon substrate to expose a part of the silicon substrate; (c) forming a first silicon oxide layer in the part of the silicon substrate which is exposed; and (d) removing the mask layer and the first silicon oxide layer, so as to form a recess in the silicon substrate.

Abstract: A submount for a light emitting diode and a method for fabricating the same are provided. The method includes the following steps: (a) providing a silicon substrate; (b) forming a mask layer on the silicon substrate to expose a part of the silicon substrate; (c) forming a first silicon oxide layer in the part of the silicon substrate which is exposed; and (d) removing the mask layer and the first silicon oxide layer, so as to form a recess in the silicon substrate.

Abstract: A silicon submount for a light emitting diode (LED) including a silicon base, a first insulating layer, a first electrode, a second electrode, and a reflective layer is provided. The silicon base has an upper surface and a lower surface, and a recess is disposed at the upper surface. The first insulating layer covers the upper surface and the lower surface of the silicon base. The first electrode and the second electrode are disposed on the first insulating layer on a bottom of the recess. The reflective layer is disposed on the first insulating layer on a sidewall of the recess. The first electrode, the second electrode, and the reflective layer are separated from one another and formed by the same material.

Abstract: A reduced surface field (RESURF) structure and a lateral diffused metal oxide semiconductor (LDMOS) device including the same are provided. The RESURF structure includes a substrate of a first conductivity type, a deep well region of a second conductivity type, an isolation structure, at least one trench insulating structure, and at least one doped region of the first conductivity type. The deep well region is disposed in the substrate. The isolation structure is disposed on the substrate. The trench insulating structure is disposed in the deep well region below the isolation structure. The doped region is disposed in the deep well region and surrounds a sidewall and a bottom of the trench insulating structure.

Abstract: A power LDMOS device including a substrate, source and drain regions, gates and trench insulating structures is provided. The substrate has a finger tip area, a finger body area and a palm area. The source regions are in the substrate in the finger body area and further extend to the finger tip area. The neighboring source regions in the finger tip area are connected. The outmost two source regions further extend to the palm area and are connected. The drain regions are in the substrate in the finger body area and further extend to the palm area. The neighboring drain regions in the palm area are connected. The source and drain regions are disposed alternately. A gate is disposed between the neighboring source and drain regions. The trench insulating structures are in the substrate in the palm area and respectively surround ends of the drain regions.

Abstract: A semiconductor device including a substrate, an epitaxial layer, a first sinker, a transistor, a diode unit, a first buried layer, and a second buried layer is provided. When the semiconductor device is operated at the high voltage, the highly large substrate current due to the external load is avoided through the diode unit disposed in the semiconductor device of an embodiment consistent with the invention. Furthermore, according to the design of the semiconductor device, the issue of the narrow input voltage range is improved, and interference of the semiconductor device with the other semiconductor devices is prevented.

Abstract: A semiconductor device including a substrate, an epitaxial layer, a first sinker, a transistor, a diode unit, a first buried layer, and a second buried layer is provided. When the semiconductor device is operated at the high voltage, the highly large substrate current due to the external load is avoided through the diode unit disposed in the semiconductor device of an embodiment consistent with the invention. Furthermore, according to the design of the semiconductor device, the issue of the narrow input voltage range is improved, and interference of the semiconductor device with the other semiconductor devices is prevented.

Abstract: An erasing method of a non-volatile memory is provided. The non-volatile memory includes a control gate disposed in a substrate, a floating gate, a gate oxide layer disposed between the floating gate and the substrate, a source region disposed in the substrate, a drain region disposed in the substrate, a first dielectric layer disposed on the floating gate, a second dielectric layer disposed on sidewalls of the floating gate, and an erase gate. The erasing method includes applying a first voltage on the control gate, applying a second voltage on the drain, applying a third voltage on the source, applying a fourth voltage on the erase gate, and applying a fifth voltage on the substrate, such that electrons are drawn from the floating gate to the erase gate to be erased.

Abstract: A semiconductor device comprising the following. A structure having: a capacitor; a first resistor; and a second resistor each within at least a portion of an oxide structure and a metal-oxide semiconductor electrode not within at least a portion of the oxide structure. The capacitor comprising: a lower capacitor first doped polysilicon portion; a capacitor interpoly oxide film portion thereover; and an upper capacitor second doped polysilicon portion over at least a portion of the capacitor interpoly oxide film portion. The first resistor comprising a lower first resistor first doped polysilicon portion and an upper first resistor second doped polysilicon portion thereover. The second resistor comprising a lower second resistor first doped polysilicon portion and an upper interpoly oxide film portion thereover. The metal-oxide semiconductor electrode comprising a lower metal-oxide semiconductor first doped polysilicon portion and an upper metal-oxide semiconductor second doped polysilicon portion thereover.

Abstract: A manufacturing method of a non-volatile memory includes first providing a substrate for defining multiple pairs of active regions; forming a control gate in one of each pair of the active regions of the substrate; sequentially forming a gate oxide layer, a conductor layer, and a patterned mask layer on the substrate, wherein the patterned mask layer exposes a portion of the conductor layer; forming a first dielectric layer on the exposed portion of the conductor layer; removing the patterned mask layer; removing the conductor layer without covering the first dielectric layer, and using the remained conductor layer as the floating gate; forming a second dielectric layer on sidewalls of the floating gate; forming an erase gate above the floating gate and correspondingly above the control gate, and forming a source region and a drain region in the other one of each pair of the active regions.

Abstract: A semiconductor device includes a substrate, an epitaxial layer, a sinker, an active device, a first buried layer, and a second buried layer. The substrate has a first type conductivity. The epitaxial layer has a second type conductivity, and is located on the substrate. The sinker has the second type conductivity, and is located in the epitaxial layer. The sinker extends from the substrate to an upper surface of the epitaxial layer, and partitions a region off from the epitaxial layer. The active device is located within the region. The first buried layer has the first type conductivity, and is located between the region and the substrate. The second buried layer has the second type conductivity, and is located between the first buried layer and the substrate. The second buried layer connects with the sinker. Because of the above-mentioned configuration, latch-up can be prevented.

Abstract: A method of fabricating an MOS device is described. A substrate doped a first type dopant is provided as a drain. A first type epitaxial layer is formed on the substrate and is patterned with a trench to form several islands. A gate dielectric layer is then formed on the surface of the trench, and a gate is formed in the trench covering the gate dielectric layer. A second type dopant is doped into the islands with the doping concentration decreasing gradually from the bottom to the top of the islands. Afterwards, a source is formed at the top of the islands. Accordingly, the doping concentration in the islands decreases gradually from the drain to the source with the highest doping concentration near the drain. Therefore, the width of the depletion region can be reduced, and the length of the device channel can be reduced for lowering channel resistance and gate capacitance.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first epitaxial layer, a first sinker, a first buried layer, a second epitaxial layer, a second sinker and a second buried layer. The first and second epitaxial layers are disposed sequentially on the substrate. The first sinker and the first buried layer define a first area from the first and the second epitaxial layers. The second sinker and the second buried layer define a second area from the second epitaxial layer in the first area. An active device is disposed in the second area. The first buried layer is disposed between the first area and the substrate, and is connected to the first sinker. The second buried layer is disposed between the second area and the first epitaxial layer, and is connected to the second sinker.

Abstract: A non-volatile memory is provided, including a control gate, a floating gate, a gate oxide layer, a source region, a drain region, a first dielectric layer, a second dielectric layer, and an erase gate. The control gate is disposed in a substrate. The floating gate comprising a coupling part and a gate part is disposed over the control gate and located over a portion of the substrate with the gate oxide layer there-between. The source region adjoins with one side of the gate part, while the drain region adjoins with the other side of the gate part. The first dielectric layer is disposed on the floating gate. The second dielectric layer is disposed on the sidewalls of the floating gate. The erase gate is disposed over the coupling part of the floating gate and covers the first dielectric layer and the second dielectric layer.

Abstract: An erasing method of a non-volatile memory is provided. The non-volatile memory includes a control gate disposed in a substrate, a floating gate, a gate oxide layer disposed between the floating gate and the substrate, a source region disposed in the substrate, a drain region disposed in the substrate, a first dielectric layer disposed on the floating gate, a second dielectric layer disposed on sidewalls of the floating gate, and an erase gate. The erasing method includes applying a first voltage on the control gate, applying a second voltage on the drain, applying a third voltage on the source, applying a fourth voltage on the erase gate, and applying a fifth voltage on the substrate, such that electrons are drawn from the floating gate to the erase gate to be erased.