Abstract: A semiconductor device comprising the following. A structure having: a capacitor; a first resistor; and a second resistor each within at least a portion of an oxide structure and a metal-oxide semiconductor electrode not within at least a portion of the oxide structure. The capacitor comprising: a lower capacitor first doped polysilicon portion; a capacitor interpoly oxide film portion thereover; and an upper capacitor second doped polysilicon portion over at least a portion of the capacitor interpoly oxide film portion. The first resistor comprising a lower first resistor first doped polysilicon portion and an upper first resistor second doped polysilicon portion thereover. The second resistor comprising a lower second resistor first doped polysilicon portion and an upper interpoly oxide film portion thereover. The metal-oxide semiconductor electrode comprising a lower metal-oxide semiconductor first doped polysilicon portion and an upper metal-oxide semiconductor second doped polysilicon portion thereover.

Abstract: A method of simultaneously forming at least: one capacitor two resistors and one metal-oxide semiconductor. A first doped polysilicon layer/patterned interpoly oxide film/second doped polysilicon layer is formed over an exposed oxide structure. The patterned interpoly oxide forms a capacitor interpoly portion within a capacitor region and a second interpoly portion within a second resistor region. A second doped polysilicon layer is formed over the structure. The doped first and second polysilicon layers are patterned to form: a lower capacitor doped first polysilicon portion and an overlying upper capacitor second doped polysilicon portion; a lower first resistor first polysilicon portion and an upper, overlying first resistor second polysilicon portion; a lower second resistor first polysilicon portion; and a lower metal-oxide semiconductor first polysilicon portion and an overlying metal-oxide semiconductor second polysilicon portion.

Abstract: A process for reducing the risk of removing metal from an underlying metal structure during a dry etch procedure used to define a borderless, overlying metal line structure, has been developed. After formation of a damascene type, underlying metal structure, deposition of an metal layer and of an overlying silicon oxide layer, is performed. A photoresist shape is used as an etch mask to allow formation of a partially etched metal line structure to be accomplished in the silicon oxide layer, and in a top portion of the metal layer. Insulator spacers are then formed on the sides of the partially etched metal line structure, resulting in a wider, partially etched metal line structure. The hard mask now presented by the defined silicon oxide component of the partially etched metal line structure, is then used as an etch mask allowing a final metal line structure, wider than the partially etched metal line structure, to be obtained.

Abstract: The present invention relates generally to semiconductor fabrication and more specifically to simultaneous formation of capacitors, resistors and metal oxide semiconductor.

Abstract: A method of fabricating an RF lateral MOS device, comprising the following steps. A substrate having a gate oxide layer formed thereover is provided. A first layer of polysilicon is formed over the gate oxide layer. A second layer of material is formed over the polysilicon layer. The polysilicon and the second layer of material are patterned to form a gate having exposed sidewalls with the gate having a lower patterned polysilicon layer and an upper patterned second material layer. Sidewall spacers are formed on the exposed sidewalls of the gate. The upper patterned second material layer of the gate is removed to form a cavity above the patterned polysilicon layer and between the sidewall spacers. A planarized copper plug is formed within the cavity.

Abstract: Using current technology, the only way to further increase device density is to decrease device pitch. The present invention achieves this by introducing a sidewall doping process that effectively reduces the source width, and hence the pitch. This sidewall doping process also eliminates the need for a source implantation mask while the sidewall spacer facilitates silicide formation at the source, the P body contact, and the polysilicon gate simultaneously. Since the source and P body are fully covered by silicide, the contact number and contact resistance can be minimized. The silicided polysilicon gate has a low sheet resistance of about 4-6 ohm/square, resulting in a higher operating frequency.

Abstract: A process for fabricating a bipolar junction transistor, featuring an N type, polysilicon emitter structure, located in an emitter trench, and featuring a narrow width. P type base region, located directly underlying an N type, emitter region, which is formed in the semiconductor substrate, along the vertical and horizontal sides of the emitter trench, has been developed. The process features forming an emitter trench in a semiconductor substrate, followed by a large angle ion implantation procedure, used to form a P type, base region, in an area of the semiconductor substrate located along the sides of the emitter trench. Formation of a polysilicon emitter structure, followed by an anneal cycle, create a narrow width, emitter region, underlying the polysilicon emitter structure, also resulting in the formation of a narrow width, P type base region, located between the overlying N type emitter region, and an underlying N type, epitaxial silicon layer.