Abstract: Manufacture of multi-junction solar cells, and devices thereof, are disclosed. The architectures are also adapted to provide for a more uniform and consistent fabrication of the solar cell structures, leading to improved yields, greater efficiency, and lower costs. Certain solar cells may be from a different manufacturing process and further include one or more compositional gradients of one or more semiconductor elements in one or more semiconductor layers, resulting in a more optimal solar cell device. A multi-junction cell may include a back surface field layer, a tunneling junction layer, a first active cell, and a second active cell.
Type:
Grant
Filed:
August 18, 2017
Date of Patent:
May 7, 2019
Assignee:
EpiWorks, Inc.
Inventors:
David Ahmari, Swee Lim, Shiva Rai, David Forbes
Abstract: Manufacture of multi junction solar cells, and devices thereof, are disclosed. The architectures are also adapted to provide for a more uniform and consistent fabrication of the solar cell structures, leading to improved yields, greater efficiency, and lower costs. Certain solar cells may be from a different manufacturing processes and further include one or more compositional gradients of one or more semiconductor elements in one or more semiconductor layers, resulting in a more optimal solar cell device.
Type:
Grant
Filed:
December 19, 2014
Date of Patent:
May 15, 2018
Assignee:
EpiWorks, Inc.
Inventors:
David Ahmari, Swee Lim, Shiva Rai, David Forbes
Abstract: Manufacture of multi-junction solar cells, and devices thereof, are disclosed. The architectures are also adapted to provide for a more uniform and consistent fabrication of the solar cell structures, leading to improved yields and lower costs. Certain solar cells may further include one or more compositional gradients of one or more semiconductor elements in one or more semiconductor layers, resulting in a more optimal solar cell device.
Type:
Grant
Filed:
June 21, 2013
Date of Patent:
February 10, 2015
Assignee:
EpiWorks, Inc.
Inventors:
David Ahmari, Swee Lim, Shiva Rai, David Forbes
Abstract: A heterojunction bipolar transistor (HBT), having a substrate formed of indium phosphide (InP), and having emitter, base and collector layers formed over the substrate such that the base layer is disposed between the emitter and collector layers. The collector layer formed from InGaAs, and the collector layer being doped n-type. The emitter layer formed from InP, and the emitter layer being doped n-type. The base layer formed of indium gallium arsenide (InGaAs) and grown by MOCVD, the base layer being tensile strained and graded, and the base layer being doped p-type with carbon. A lattice mismatch, for at least a portion of the base layer, between the substrate and the base material is greater than 0.2%.