Abstract: A command processing method and a storage controller using the same are provided. The command processing method includes: receiving a plurality of I/O commands; categorizing the I/O commands into a plurality of groups according to a processor effort index of the I/O commands; selecting a first group from the groups, resetting a timer and obtaining an expiration time corresponding to the first group according to the I/O commands of the first group, and executing the I/O commands of the first group; and selecting a second group from the groups and resetting the timer when the expiration time of the first group expires, wherein when the processor effort index of the first group is less than a threshold, a clock frequency of the processor is lowered before the expiration time expires.

Abstract: A valid data management method and a storage controller are provided. The method includes creating a valid data mark table and a valid logical addresses table corresponding to a target physical unit according to a logical-to-physical table and a target physical-to-logical table corresponding to the target physical unit, wherein the valid data mark table records a plurality of mark values respectively corresponding to a plurality of target logical addresses, the mark values respectively indicate whether the corresponding logical addresses is valid or invalid, and the valid logical addresses table only records one or more valid target logical addresses according to an order of one or more first bit values in the valid data mark table; and identifying one or more valid data of the target physical unit according to the logical-to-physical table, the valid data mark table and the valid logical addresses table corresponding to the target physical unit.

Abstract: A data encoding method, a data decoding method, and a storage controller are provided. The encoding method includes: obtaining a verification data corresponding to a raw data according to a write command; adding the verification data to the raw data, and obtaining a scrambled data accordingly; and performing an encoding operation on the scrambled data to obtain a codeword data. The decoding method includes: performing a decoding operation on a codeword data to obtain a decoded codeword data, and obtaining a pre-scrambling data accordingly; identifying a verification data and a raw data in the pre-scrambling data; identifying one or more first system data corresponding to the raw data according to a read command; and determining whether the raw data is correct by comparing the one or more first system data and the verification data.

Abstract: A memory management method and a storage controller are provided. The method includes performing a decoding operation to a first data stored in a first word line among multiple word lines of a rewritable non-volatile memory module to determine whether the decoding operation is successful or failed, and obtain a first error value of the first word line; when the decoding operation is determined as successful, determining whether to mark the first word line as a bad word line according to the first error value and a first threshold; and when the decoding operation is determined as failed, obtaining a second error value of a second word line adjacent to the first word line, and determining whether to mark both of the first and second word lines as the bad word line according to the first error value, the second error value, and a first threshold.

Abstract: A data reading method and a storage controller for a rewritable non-volatile memory module are provided. The method includes identifying a plurality of preset bit values corresponding to a plurality of first memory cells of a first physical unit; reading the first memory cells by respectively using a plurality of preset read voltages to obtain a plurality of read bit values corresponding to the first memory cells; adjusting the preset read voltages based on the identified preset bit values and the read bit values corresponding to the first memory cells to obtain a plurality of optimized read voltages; and executing a read command sequence on the first physical unit by using the optimized read voltages.

Abstract: A data backup method is provided. The data backup method includes maintaining a logical-to-physical table (L2P table) in a memory, where the L2P table records a plurality of physical addresses respectively corresponding to a plurality of first logical addresses and a plurality of trim marks; receiving a trim command, wherein the trim command indicates that data stored in one or more second logical addresses is invalid; according to the trim command, not clearing physical addresses respectively corresponding to the second logical addresses in the L2P table, and changing trim marks respectively corresponding to the second logical addresses from a first bit value to a second bit value; and when a predetermined condition is met, updating the L2P table according to the trim marks, and storing the updated L2P table into a rewritable non-volatile memory module.

Abstract: A data writing method is provided. The method includes writing a first write data into a first physical sub-unit in a storage device according to a first write command; recording a first meta data corresponding to the first write data into the storage device; writing a second write data into a second physical sub-unit in the storage device; recording a second meta data corresponding to the second write data into the storage device. A second write identification code of the second meta data is set to be different from a first write identification code of the first meta data if the second physical unit is closely adjacent to the first physical unit and the second write data is written according to the second write command; and whether the second write data is valid or invalid is determined according to the second meta data if a special event occurs.

Abstract: A data writing method is provided. The method includes writing a first write data into a first physical sub-unit in a storage device according to a first write command; recording a first meta data corresponding to the first write data into the storage device; writing a second write data into a second physical sub-unit in the storage device; recording a second meta data corresponding to the second write data into the storage device. A second write identification code of the second meta data is set to be different from a first write identification code of the first meta data if the second physical unit is closely adjacent to the first physical unit and the second write data is written according to the second write command; and whether the second write data is valid or invalid is determined according to the second meta data if a special event occurs.

Abstract: A decoding method for low density parity code is provided. The method includes performing an iterative decoding operation for a codeword, wherein a plurality of Log-Likelihood-Ratios correspond respectively to a plurality of data bits of the codeword; determining whether the iterative decoding operation is successful; determining whether a perturbation condition is met if the iterative decoding operation is not successful; performing protect operation for a first Log-Likelihood-Ratio among the Log-Likelihood-Ratios, and performing a perturbation operation for a plurality of second Log-Likelihood-Ratios among the Log-Likelihood-Ratios, wherein the second Log-Likelihood-Ratios are different to the first Log-Likelihood-Ratio; and re-performing the iterative decoding operation for the codeword after finishing the perturbation operation.

Abstract: A decoding method, a memory storage device and a memory control circuit unit are provided. The decoding method includes: reading memory cells based on a default hard-decision voltage level and decoding the obtained hard-bit information; if the decoding fails, reading the memory cells based on default soft-decision voltage levels and then decoding the obtained soft-bit information; if the decoding still fails, reading the memory cells based on first test voltage levels to obtain first soft-bit information and reading the memory cells based on second test voltage levels to obtain second soft-bit information; obtaining a first estimating parameter and a second estimating parameter according to the first soft-bit information and the second soft-bit information, respectively; and updating the default hard-decision voltage level according to the first estimating parameter and the second estimating parameter. As a result, a decoding efficiency can be improved.

Abstract: A memory management method, a memory storage device and a memory control circuit unit are provided. The method includes: configuring a default encoding rule for a first physical erasing unit which includes encoding data to be stored to the first physical erasing unit based on a default code rate; configuring a first encoding rule, for the first physical erasing unit according to error estimating information of the first physical erasing unit, which includes encoding data to be stored to a first-type physical programming unit and a second-type physical programming unit belonging to the first physical erasing unit based on a first code rate and a second code rate respectively, where a value of the first code rate is greater than a value of the default code rate, and a value of the second code rate is less than the value of the default code rate.

Abstract: A memory management method is provided. The method includes writing a plurality of first data into a first physical block and storing a first stamp corresponding to the first physical block; writing a plurality of second data into a second physical block and storing a second stamp corresponding to the second physical block, wherein the second stamp is greater than the first stamp; moving a plurality of third data in the first data in the first physical block to a third physical block, wherein the third data are valid data and the third data match a specific type; and storing a third stamp corresponding to the third physical block and updating the second stamp corresponding to the second physical block to a fourth stamp, wherein the fourth stamp is greater than the third stamp and the third stamp is greater than or equal to the second stamp.

Abstract: A decoding method, a memory storage device and a memory control circuit unit are provided. The decoding method includes: reading a target physical unit based on a first read voltage level; performing a first decoding operation; reading an authentication physical unit based on a first candidate voltage level to obtain first assistance data and reading the authentication physical unit based on a second candidate voltage level to obtain second assistance data if the first decoding operation fails; obtaining a first estimation parameter according to the first assistance data and authentication data and obtaining a second estimation parameter according to the second assistance data and the authentication data; determining a second read voltage level according to the first estimation parameter and the second estimation parameter; and reading the target physical unit again based on the second read voltage level. Accordingly, the decoding efficiency may be improved.

Abstract: A data transmission method, a memory storage device and a memory control circuit unit are provided. The method includes: obtaining a first command from a host system and counting a first time value; performing a first access operation corresponding to the first command on the rewritable non-volatile memory module; and generating a first completion message corresponding to completion of the first access operation and buffering the first completion message in a buffer area; and transmitting the first completion message buffered in the buffer area to the host system if the first time value meets a first waiting time value. Accordingly, a data access speed detected by the host system is stabilized.

Abstract: A data transmission method, a memory storage device and a memory control circuit unit are provided. The method includes: obtaining a first command from a host system and counting a first time value; performing a first access operation corresponding to the first command on the rewritable non-volatile memory module; and generating a first completion message corresponding to completion of the first access operation and buffering the first completion message in a buffer area; and transmitting the first completion message buffered in the buffer area to the host system if the first time value meets a first waiting time value. Accordingly, a data access speed detected by the host system is stabilized.

Abstract: A data transmission method is provided. The method includes receiving a transmission command from a host system, wherein the transmission command includes a starting logical block address, a number of logical blocks, a first physical region page pointer, and a second physical region page pointer, wherein the transmission command is configured to transmit target data between at least one target logical block of a rewritable non-volatile memory module and at least one target memory page of a host memory; buffering a plurality of entries of at least one physical region page pointer list corresponding to the transmission command if the second physical region page pointer is a first list starting address of a first physical region page pointer list corresponding to the transmission command; and transmitting corresponding data according to the buffered entries.

Abstract: A data reading method is provided. The method includes receiving a read command from a host system, wherein the read command includes a starting logical block address, a number of logical blocks, a first physical region page pointer, and a second physical region page pointer, and the read command is configured to read target data from at least one target logical block of a rewritable non-volatile memory module and write the read target data into at least one target memory page of a host memory; obtaining an address of each of the target memory pages respectively corresponding to the at least one target logical block according to the read command; and selecting a first target logical block from the at least one target logical block, and writing the read first target data into a first target memory page according to the obtained address of the first target memory page.

Abstract: A memory management method, a memory storage device and a memory control circuit unit are provided. The method includes: configuring a default encoding rule for a first physical erasing unit which includes encoding data to be stored to the first physical erasing unit based on a default code rate; configuring a first encoding rule, for the first physical erasing unit according to error estimating information of the first physical erasing unit, which includes encoding data to be stored to a first-type physical programming unit and a second-type physical programming unit belonging to the first physical erasing unit based on a first code rate and a second code rate respectively, where a value of the first code rate is greater than a value of the default code rate, and a value of the second code rate is less than the value of the default code rate.

Abstract: A decoding method, a memory storage device, and a memory control circuit unit are provided. The decoding method includes: reading a codeword from a memory module and estimating error level information of the codeword; inputting the codeword and the error level information to an error checking and correcting circuit through a first message channel and a second message channel respectively; determining whether the error level information meets a default condition; if yes, inputting the codeword to a first decoding engine of the error checking and correcting circuit for decoding; otherwise, inputting the codeword to a second decoding engine of the error checking and correcting circuit for decoding, wherein a power consumption of the first decoding engine is lower than that of the second decoding engine, and a decoding success rate of the first decoding engine is lower than that of the second decoding engine. Therefore, an operating flexibility for decoding may be improved.

Abstract: A decoding method for low density parity code is provided. The method includes performing an iterative decoding operation for a codeword, wherein a plurality of Log-Likelihood-Ratios correspond respectively to a plurality of data bits of the codeword; determining whether the iterative decoding operation is successful; determining whether a perturbation condition is met if the iterative decoding operation is not successful; performing protect operation for a first Log-Likelihood-Ratio among the Log-Likelihood-Ratios, and performing a perturbation operation for a plurality of second Log-Likelihood-Ratios among the Log-Likelihood-Ratios, wherein the second Log-Likelihood-Ratios are different to the first Log-Likelihood-Ratio; and re-performing the iterative decoding operation for the codeword after finishing the perturbation operation.