Patents Assigned to Ergo Computing, Inc.
  • Patent number: 5289342
    Abstract: The system includes a circuit board on which electrical components are mounted. The components are mounted on the front side of the board, and the back side of the board is thermally coupled to the housing by a liquid-filled thermal heat sink pouch between the board and the housing. A heat generating component such as a microprocessor is mounted to the front side of the board, but the top surface of the component is directed toward the back side of the board such that it is also thermally coupled to the housing.
    Type: Grant
    Filed: November 9, 1992
    Date of Patent: February 22, 1994
    Assignee: Ergo Computing, Inc.
    Inventors: Tom J. Spalding, Keith E. Kowal, James H. Bleck, Scott H. Wakefield, John E. Thrailkill
  • Patent number: 5187645
    Abstract: A microcomputer system includes a microprocessor and a housing for holding the microprocessor. The housing includes sets of conectors preferably comprised of two alternative sets of connectors. The microcomputer system is light weight, small and portable. Connections to external components such as peripheral devices are achieved with one embodiment via a docking connector. This docking connector includes a set of pin connectors that can be coupled to connectors on the housing. It also includes an ejector mechanism. The ejector mechanism enables decoupling by depression of the ejector. The use of the docking connector allows all peripheral connections to be realized through a single connector.
    Type: Grant
    Filed: June 7, 1991
    Date of Patent: February 16, 1993
    Assignee: Ergo Computing, Inc.
    Inventors: Tom J. Spalding, Keith E. Kowal, James H. Bleck, Scott H. Wakefield, John E. Thrailkill
  • Patent number: 5123095
    Abstract: A vector processor is closely integrated with a scalar processor. The scalar processor provides virtual-to-physical memory translation for both scalar and vector operations. In vector operations, a block move operation preformed by the scalar processor is intercepted, the write command in the operation is converted to a read, and data resulting from a vector operation is returned to the address specified by the block move write command. Writing of the data may be masked by a prior vector operation. Prefetch queues and write queues are provided between main memory and the vector processor. A microinstruction interface is supported for the vector processor.
    Type: Grant
    Filed: January 17, 1989
    Date of Patent: June 16, 1992
    Assignee: Ergo Computing, Inc.
    Inventors: Gregory M. Papadopoulos, David E. Culler, James T. Pinkerton
  • Patent number: D336075
    Type: Grant
    Filed: June 7, 1991
    Date of Patent: June 1, 1993
    Assignee: Ergo Computing, Inc.
    Inventors: Scott H. Wakefield, John E. Thraikill, Tom J. Spalding, Keith E. Kowal, James H. Bleck