Patents Assigned to Esencia Technologies Inc.
  • Method and apparatus for the definition and generation of configurable, high performance low-power embedded microprocessor cores
    Patent number: 9329872
    Abstract: A system and method for configuring a microprocessor core may allow a microprocessor core to be configurable. Configuration may be dynamic or automatic using an application program. Microprocessor memory, decoding units, arithmetic logic units, register banks, storage, register bypass units, and a user interface may be configured. The configuration may also be used to optimize an instruction set to run on the microprocessor core.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: May 3, 2016
    Assignee: ESENCIA TECHNOLOGIES INC.
    Inventors: Miguel A. Guerrero, Alpesh B. Oza
  • Method for Improving Performance of a Pipelined Microprocessor by Utilizing Pipeline Virtual Registers
    Publication number: 20130332704
    Abstract: A method for improving performance of a pipelined microprocessor by utilizing pipeline virtual registers allows for either decreased register spillage or decreased area and power consumption of a microprocessor. The microprocessor takes advantage of register bypass logic to write short-lived values to virtual registers, which are discarded instead of being written to the register bank, thus reducing register pressure by avoiding short-lived values being written to the register bank.
    Type: Application
    Filed: June 10, 2013
    Publication date: December 12, 2013
    Applicant: ESENCIA TECHNOLOGIES INC.
    Inventor: Miguel A Guerrero
  • Method and Apparatus for the Definition and Generation of Configurable, High Performance Low-Power Embedded Microprocessor Cores
    Publication number: 20130290692
    Abstract: A system and method for configuring a microprocessor core may allow a microprocessor core to be configurable. Configuration may be dynamic or automatic using an application program. Microprocessor memory, decoding units, arithmetic logic units, register banks, storage, register bypass units, and a user interface may be configured. The configuration may also be used to optimize an instruction set to run on the microprocessor core.
    Type: Application
    Filed: April 29, 2013
    Publication date: October 31, 2013
    Applicant: Esencia Technologies Inc.
    Inventors: MIguel A. GUERRERO, Alpesh B. OZA
  • Method and Apparatus for the Automatic Generation of RTL from an Untimed C or C++ Description as a Fine-Grained Specialization of a Micro-processor Soft Core
    Publication number: 20130290693
    Abstract: A system and method for configuring a configuring a register transfer level description from a programming language may utilize a configurable microprocessor core. A compiler may compile the programming language using performance statistics and user constraints. A template processor may translate the programming language into register transfer level description language using template files. Timing and area constraints may be used prior to output a gate level netlist ready to place on a microchip.
    Type: Application
    Filed: May 10, 2013
    Publication date: October 31, 2013
    Applicant: ESENCIA TECHNOLOGIES INC.
    Inventors: Miguel A. Guerrero, Alpesh B. Oza