Abstract: The prior art requires the selective removal of antifuse material from the bottom of the standard via. This cannot always be accomplished without damage to the nearby antifuse. In addition in the absence of antifuse structural isolation, problems were encountered at M2 etch in consistently removing the full thickness of metallic material at this level. Shorting due to underetch was often encountered. These problems were solved by first forming only the antifuse via. This allowed the via to be controlled and optimized for antifuse requirements and for the antifuse material to be patterned without regard to possible side effects on the standard vias. Design rules for overlaps of overfuse and M2 layers were amended such that each antifuse is individually isolated. The latter were then formed, without (as in the prior art) any concerns that the antifuse might be affected.

Abstract: A process for defining uniform contact hole openings in an insulator layer, and in a top portion of a conductive layer, has been developed. The process features a series of isotropic and anisotropic, dry etch procedures, used to define an initial contact hole opening in the insulator layer, and in the top portion of the conductive region. The isotropic dry etch procedure results in a tapered contact hole profile for top portion of the initial contact hole opening, while subsequent anisotropic dry etch procedures create a straight walled contact hole profile for the bottom portion of the initial contact hole opening. After removal of the contact hole defining, photoresist shape, a wet etch procedure is used to laterally recess-the insulator layer exposed in the initial contact hole opening creating the final, uniform contact hole opening.

Abstract: A process for defining uniform contact hole openings in an insulator layer, and in a top portion of a conductive layer, has been developed. The process features a series of isotropic and anisotropic, dry etch procedures, used to define an initial contact hole opening in the insulator layer, and in the top portion of the conductive region. The isotropic dry etch procedure results in a tapered contact hole profile for top portion of the initial contact hole opening, while subsequent anisotropic dry etch procedures create a straight walled contact hole profile for the bottom portion of the initial contact hole opening. After removal of the contact hole defining, photoresist shape, a wet etch procedure is used to laterally recess the insulator layer exposed in the initial contact hole opening creating the final, uniform contact hole opening.

Abstract: Methods of forming a gate dielectric layer, and a composite gate dielectric layer, for a thin film transistor, has been developed. A first embodiment of this invention describes the procedure used to create the composite gate dielectric layer. A first, thin silicon oxide gate dielectric layer is thermally grown on an underlying active semiconductor layer, such as polysilicon. A first anneal procedure, is performed at a temperature greater than the temperature used for the thermal growth of this layer, resulting in improved parametric integrity. A thicker, second silicon oxide gate dielectric layer is then thermally deposited, followed by an anneal procedure used to provide a composite gate dielectric layer comprised of a densified, thermally deposited second silicon oxide gate dielectric layer, on an underlying, thermally grown first silicon oxide gate dielectric layer.

Abstract: A P channel high voltage metal oxide semiconductor device is described which is integrated in the same chip or wafer as standard P channel and N channel metal oxide semiconductor devices. The high voltage device has a lightly doped p− drift region adjacent to the heavily doped p+ drain region. A high voltage support region is formed directly below the drift region using high energy ion implantation with an implantation energy of between about 2 and 3 Mev. This high energy ion implantation is used to precisely locate the high voltage support region directly below the drift region. This high voltage support region avoids punch-through from the P channel drain through the drift region into the substrate while using a standard depth for the n type well. This allows the high voltage device to be integrated into the same chip or wafer as standard P channel and N channel metal oxide semiconductor devices.