Abstract: An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit.

Abstract: A ring oscillator having an odd number of active elements connected in series, where the signal output of one active element is connected to the signal input of the next active element to form a closed ring of active elements. Each active element has a power supply input and a ground connection, a signal input and a signal output, an inverter sub-element having a pair of current mirrors, and a capacitor controlled bias sub-element.

Abstract: A system is provided for use in an audio signal processor to reduce the order of the loop to remove sound artifacts from an audio signal that includes an input for receiving an audio input signal a control loop of order greater than one configured to process the audio input signal and to output a Pulse Width Modulated audio output signal, a circuit for performing a gradual reduction of the order of the control loop such that prior to entering a shut down state the order is reduced to a single order and a circuit to disconnect a Driver Circuit from the Pulse Width modulated signal operated by a timing device designed to switch at the moment of zero average output value.

Abstract: The invention has been described in the context of a system and method of removing artifacts from an audio signal during shutdown of the output. The system includes a means by which the average value may be found to be zero or sufficiently close to zero as determined by the resolution of the filter output and a means by which the filter average value being zero or close to zero is used to disconnect (or equivalently change impedance or power) of the device or devices rendering the PWM signal into the analog domain as may be implemented by a Class D bridge chip and disconnection means. The invention further includes a means by which channels are in succession compared to prior channels and switched to share the fixed output signal and a means by which upon finding the last channel is at the zero average value in synchrony with the prior channel or channels the output of the entire group of channels may be simultaneously disconnected.

Abstract: The invention has been described in the context of a system and method of removing artifacts from an audio signal during shutdown of the output. The system includes a means by which the average value may be found to be zero or sufficiently close to zero as determined by the resolution of the filter output and a means by which the filter average value being zero or close to zero is used to disconnect (or equivalently change impedance or power) of the device or devices rendering the PWM signal into the analog domain as may be implemented by a Class D bridge chip and disconnection means.

Abstract: An electrical isolation barrier for use in a Data Access Arrangement uses a high frequency (HF) transformer 24 to provide isolation. An input signal, which may be analog or digital, is connected to a modulator. The analog output of the modulator is connected to the input of the HF transformer. The output of the HF transformer is connected to the input of a demodulator. Simple amplitude modulation can be used in the modulator to modulate the input signal to the frequency range of operation of the HF transformer. A simple low pass filter may be incorporated in the demodulator to remove harmonic distortion caused by the HF transformer. The output signal of the demodulator is substantially the same as input signal.

Abstract: A system and method are provided for compensating for output error in a sigma delta circuit. The system includes an input for receiving an input signal and an output configured to output a output signal. The system further includes a summation component configured to add a first error voltage value, which is derived from an output signal, to an incoming input signal, and a subtraction component configured to subtract a second error voltage value, where the second error voltage value is derived from the adding of a first error voltage value to an incoming input signal.

Abstract: The invention is directed to a bi-quad filter circuit configured with sigma-delta devices that operate as binary rate multipliers (BRMs). Unlike conventional bi-quad filter circuits, the invention provides a bi-quad filter configured with a single-bit BRM. In another embodiment, the invention further provides a bi-quad filter configured with multiple-bit BRMs.

Abstract: An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit.

Abstract: A system and method are provided for measuring tilt of a sensor die with respect to the optical axis of the lens assembly in a camera module by providing a camera module having a sensor die with a plurality of focal indicial located on a surface, and a lens or lens assembly adjustably held about the sensor die and having an optical axis; exposing the lens to light; measuring the focus of each focal indicia with respect to the position of the lens; and calculating the tilt of the sensor die with respect to the optical axis of the lens.

Abstract: An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit.

Abstract: A system and method are provided for automatically setting the focus of a camera assembly; providing a camera assembly having a sensor die having indicia points located on a surface, a lens assembly having at least one optical lens; a lens assembly holder configured to adjustably hold the lens assembly in a position about the sensor die, and; exposing the lens assembly to a light source; automatically adjusting the lens assembly with respect to the sensor die; automatically measuring the focus of each focal indicia with respect to the positions of the lens assembly; and setting the position of the lens assembly with respect to the sensor die at an optimal position.

Abstract: A system and method are provided for signal processing between any two or more connected analog signal processing elements, including a plurality of analog processing elements connected via DC blocking capacitors and a signal processing element that operates as the source of the signal employing a controlling means to adjust its output impedance.

Abstract: A system and method are provided for encoding and compressing video data. A memory device is configured to store video data, and a corresponding memory controller controls the storage of video data in the memory device. A frame buffer compression module compresses frame data received from a video module to be stored in the memory device according to the memory controller and decompresses compressed frame data received from the memory device according to the memory controller for use by a video module. The frame buffer compression module includes a frame buffer compression encoder configured to encode and compress frame data received from a video module for storage in memory according to the memory controller. The frame buffer also includes a corresponding frame buffer compression decoder configured to decode and decompress frame data received from memory according to the memory controller for use by a video module.

Abstract: The present invention relates to multi-bit to pulse width modulated signal conversion, with extensions to digital-to-analog conversion. In particular, it has application to conversion of pulse code modulated signals, such as used in CDs and DVDs, to audio output.

Abstract: The present invention relates to digital-to-analog conversion. In particular, it has application to conversion of pulse code modulated signals, such as used in CDs and DVDs, to a pulse width modulated or analog signal.

Abstract: An image processing system comprises a processing circuitry operable to receive a digital image and a line buffer circuitry communicatively coupled to the processing circuitry, the line buffer circuitry comprising a plurality of line buffers. The processing circuitry performs cross talk correction on a first pixel during a first pass to generate a first cross talk corrected pixel, wherein said first pixel is received from a first line buffer of the plurality of line buffers. During the first pass, the processing circuitry further stores the first cross talk corrected pixel in the line buffer circuitry, retrieves the first cross talk corrected pixel from the line buffer circuitry, and uses the first cross talk corrected pixel to perform cross talk correction on a second pixel to generate a second cross talk corrected pixel, wherein the second pixel is received from a second line buffer of the plurality of line buffers.

Abstract: Disclosed are a multi-stage amplifier circuit, a method of operating a multi-stage amplifier circuit, and a device with the multi-stage amplifier circuit. The amplifier circuit technology includes an operational amplifier shared among multiple stages and switching circuitry. The various switching circuitry switches among elements to provide different input signals and different feedback to the shared operational amplifier at the different stages of operation of the amplifier circuit. The various switching circuitry also stores and discharges charge at one or more operational amplifier inputs.

Abstract: An image processing method and apparatus is described for processing a signal from a monochrome or color sensor that may be subject to pixel defects or blemishes. Without prior knowledge of any pixel defects, the processing method examines each pixel value and its neighboring pixel values. A number of tests are applied to the set of pixel values to determine whether the underlying pixel is defective. If the underlying pixel is determined to be defective, the pixel value is replaced by an estimate value derived from the values of its neighboring pixels. Otherwise, the pixel value remains intact.

Abstract: A system and method are provided for a high speed sigma delta circuit operation including a sigma-delta analog to digital converter configured to receive an input signal and to output a single digital bit representative of that signal and any associated noise. Further included is a finite impulse response filter configured to accumulate a stream of digital bits from the ADC device within a shift register, to sum a coefficient of each bit, and weigh each bit in response to a corresponding bit in the shift register. Also included is a quantizing device for receiving the summation of the weighted bits of the FIR device and rendering a representative bit as output.