Abstract: An asynchronous NAND-type memory device includes a circuit configured to perform an operation based on a signal, a first pin configured to obtain an operation control signal, a second pin configured to output a data output reference signal, and a third pin configured to output data in synchronization with the data output reference signal. The circuit is provided such that the first pin obtains, from the external device, the operation control signal that is transitioned at a second time point after a first time point at which the memory device enters into a ready state, the second pin outputs the data output reference signal, which is transitioned at a third time point that is later than the second time point by a predetermined time interval, and the third pin outputs the data in synchronization with the operation control signal which is periodically transitioned, from the third time point.