Abstract: Systems and methods for optimizing trained ML hardware models by collecting machine learning (ML) training inputs and outputs; selecting a ML model architecture from ML model architectures; training the selected ML model architecture with the ML training inputs and outputs; selecting a hardware processor from hardware processors; and creating a trained ML hardware model by inputting the selected hardware processor with the trained ML model. ML test inputs and outputs, and types of test metrics are selected and used to test the trained ML hardware model to provide runtime test metrics data for ML output predictions made by the trained ML hardware model. The trained ML hardware model is optimized to become an optimized trained ML hardware model using the runtime test metrics by selecting a new selected ML model architecture, selecting a new selected hardware processor, or updating the trained ML model using the runtime metrics test data.

Abstract: There is disclosed a self-timed processor. The self-timed processor includes a plurality of functional blocks comprising null convention logic. Each of the functional blocks outputs one or more multi-rail data values. A global acknowledge tree generates a global acknowledge signal provided to all of the plurality of functional blocks. The global acknowledge signal switches to a first state when all of the multi-rail data values output from the plurality of functional blocks are in respective valid states, and the global acknowledge signal switches to a second state when all of the multi-rail data values output from the plurality of functional blocks are in a null state.

Abstract: Automatic speech recognition (ASR) systems and methods. An ASR system includes a vector memory to store a plurality of feature vectors sequentially extracted from an audio data stream. A first neural network performs speech recognition processing on feature vectors stored in the vector memory to attempt to recognize a word from a predetermined vocabulary. A second neural network controls when the first neural network performs the speech recognition processing. The first neural network is held in a quiescent state except when performing the speech recognition processing under control of the second neural network.

Abstract: There is disclosed a self-timed clocked synchronous processor having at least one combinatorial logic (CL) block for processing data. The CL block has a critical path with a propagation delay that is a minimum allowable clock period to perform data processing of the CL block at an operating voltage of the processor without a timing error due to a register of the processor receiving the critical path output before it is completed. The processor has a critical path oscillator to simulate the critical path propagation delay and create an oscillator clock signal with a period greater than the minimum allowable clock period. The oscillator clock signal is used to clock the register, avoiding the timing error. A power manager outputs an operating voltage to the processor that causes the oscillator clock to be faster than an external time reference period for completing the current task of the processor.

Abstract: Temperature-independent clock generation systems and methods are described that include a trained neural network coupled to a frequency correction circuit that corrects a crystal resonator output of a clock signal having a frequency that changes with changes in temperature. The neural network is trained with test temperatures and corresponding temperature based changes in frequency for test resonators of the same type as the resonator of the real time clock. The neutral network is trained to output frequency corrections based on a set of measured reference temperature-based changes in frequency for the crystal resonator and a current temperature of the resonator. The frequency correction circuit receives the frequency corrections from the neural network and corrects changes in the frequency caused by the changes in temperature of the resonator to provide a clock signal having an output frequency that is independent of the current temperature of the resonator.

Abstract: Self-timed processing systems and methods of operating self-timed processing systems are disclosed. A self-timed processing system includes an asynchronous null convention logic (NCL) processor, a memory that accepts input signals on an active edge of a memory clock signal, and logic to combine a first acknowledge signal and a second acknowledge signal to generate the memory clock signal. The first acknowledge signal indicates input signals are ready to be accepted by the memory. The second acknowledge signal indicates data signals previously output from the memory have been accepted by the processor.

Abstract: There is disclosed a self-timed processor. The self-timed processor includes combinatorial logic comprising multi-rail delay insensitive asynchronous logic (DIAL) to output one or more multi-rail data values to a multiplexer. It also includes a test pattern input to output a test pattern bit stream of multi-rail test data values to the multiplexer. The multiplexer has Boolean logic to output one or more multi-rail multiplexed values to a latch. The multiplexer also has a single rail selector input to select whether the multi-rail multiplexed values are the multi-rail data values or the multi-rail test data values.

Abstract: There is disclosed a self-timed processor. The self-timed processor includes trigger logic having a trigger input to receive an event trigger signal, a data input set to data value 1, a trigger output to send a trigger output signal when the event trigger signal is received, and a reset input to reset the trigger output signal. The processor also has a delay insensitive asynchronous logic (DIAL) block with multi-rail DIAL inputs to receive a multi-rail DIAL input having a) the trigger output signal, and b) data value 0; and data phase completion logic to output a completion signal indicating an end of a data propagate phase of the DIAL block to reset the trigger output signal when multi-rail data DIAL data process values of the DIAL block reach a DIAL valid state.

Abstract: There are disclosed asynchronous computing devices and methods of operating asynchronous computing devices. An asynchronous computing device includes an asynchronous processor operative from an operating voltage and a voltage regulator circuit. The asynchronous processor includes a collection of asynchronous logic circuits that are collectively capable of executing stored instructions. The voltage regulator circuit receives a voltage request from the asynchronous processor and outputs the operating voltage to the asynchronous processor as defined by the voltage request.

Abstract: There is disclosed a self-timed processor. The self-timed processor includes a plurality of functional blocks comprising null convention logic. Each of the functional blocks outputs one or more multi-rail data values. A global acknowledge tree generates a global acknowledge signal provided to all of the plurality of functional blocks. The global acknowledge signal switches to a first state when all of the multi-rail data values output from the plurality of functional blocks are in respective valid states, and the global acknowledge signal switches to a second state when all of the multi-rail data values output from the plurality of functional blocks are in a null state.

Abstract: Voltage source circuits, asynchronous processing systems and methods are disclosed. A voltage source circuit includes a capacitor storing an operating voltage for an asynchronous processor. A frequency comparator compares a frequency reference and a feedback signal indicative of an operating frequency of the asynchronous processor to determine whether or not the operating frequency is less than a target frequency. When operating frequency is less than the target frequency, a charge pump adds charge to the capacitor.

Abstract: There are disclosed asynchronous computing devices and methods of operating asynchronous computing devices. An asynchronous computing device may include an asynchronous processor and a voltage regulator circuit that outputs an operating voltage to the asynchronous processor in response to a voltage request received from the asynchronous processor.