Abstract: A method for operating a digital computer to globally route interconnects between terminals of a gate array. A first terminal closest to an average position of terminals to be interconnected is identified. A second terminal closest to the first terminal is then identified, and a first path between the first and second terminals is established along possible paths. An edge of the first path is set as a routing path if predetermined conditions are met. A closest remaining terminal to an established path is next identified, and a shortest path between the closest terminal and the established path to which it was closest is established. Edges of the shortest path and/or the established path to which it was closest are set as routing paths, if predetermined conditions are met. The above steps are then repeated for remaining terminals to be interconnected. Any possible paths within established paths with no set edges can then be set as routing paths.

Abstract: An interrupt notice system for permitting individual ones of a plurality of operating devices to indicate to others that an interrupt of their operations is being initiated through transmitting an interrupt through a controller at a proper time. The controller provides for directing such interrupt, and for synchronizing the system.

Abstract: A method for evaluating the testability of circuit systems containing a plurality of logic gates through evaluating statistical properties in response to selected inputs.

Abstract: A clock bus system fabricated on an integrated circuit for distributing a train of clock pulses to circuit elements on the integrated circuit. An input terminal is connected to receive a train of clock pulses. All of the circuit elements are circumscribed by a clock bus which is also coupled to each of the circuit elements. A plurality of distribution legs which include clock bus drivers are coupled to the input terminal by conductors and provide the train of clock pulses to the clock bus at spaced-apart locations. The distribution legs coupled to the input terminal by shorter conductors include delay elements for delaying the clock pulse train by time periods corresponding to the delay inherent in longer conductors. The clock pulse trains provided to the clock bus by the distribution legs are thereby synchronized with respect to each other.

Abstract: A digital memory structured of interconnection substrates, input and output substrates and memory substrates affixed to a cooling insert.

Abstract: An integrated circuit with temperature compensated output buffers which are adapted for impedance matched coupling to transmission lines when operated at either room temperature or at a cryogenic temperature (e.g., immersed in liquid nitrogen). The output buffers include output terminals which are adapted to be coupled to the transmission lines. Output stages of the output buffers have an output impedance which is less than a characteristic impedance of the transmission lines, and are characterized by a temperature coefficient of resistance. Compensation resistors which have an impedance less than the characteristic impedance of the transmission lines, and are characterized by a relatively low temperature coefficient of resistance, couple the output stages to the output terminals.

Abstract: An electronic clock tuning system for a digital computer of the type including a plurality of major function circuit boards comprised of a plurality of gate arrays. A clock pulse train is produced by a master oscillator, and distributed to each major function circuit board by a master fanout. The clock pulse train is distributed throughout each major function circuit board by a local fanout. Each major function circuit board includes a plurality of electronic delay arrays, each of which distributes the clock pulse train to a group of gate arrays on the major function board, and delays the clock pulse train supplied to each gate array by one of a plurality of discrete delay periods. Each electronic delay array includes shift registers for serially receiving digital delay tuning codes and for producing digital delay select signals representative of discrete delay periods.

Abstract: A cryostat cooling system cools the central processor (CP) circuit boards of a computer to enhance the performance of the electronic components of the central processor. The cryostat includes a pair of concentrically positioned circular cylindrical shells. The inner shell is suspended from the outer shell by a thin (small cross-section) thermal isolation support ring. A vacuum chamber is formed between the inner and the outer shells. The top of the inner shell is covered by an inner shell top plate having a pair of openings through which the CP boards are inserted. A pair of containment vessels are mounted below the inner shell top plate to receive the CP boards. An inlet supply tube is connected to the containment vessel to supply liquid nitrogen. Overflow vents permit excess liquid nitrogen and nitrogen gas to flow from the containment vessels into the interior of the inner shell.

Abstract: An improved built-in self-test system fabricated on an LSI circuit chip for performing dynamic tests of main logic function operation. The built-in self-test system includes a control register comprising a series of static flip-flops connected for serial test data transfer and for producing test system control signals. An input shift register connected for serial test data transfer with the control register and for parallel test data transfer with the main logic function is formed by a series arrangement of static flip-flops. An output register connected for serial test data transfer with the input register, and for parallel test data transfer with the main logic function, is formed by a series arrangement of static flip-flops. A test clock enable signal is latched by a test clock enable latch, and gated with a system clock signal to produce input and output register clock signals. A test strobe signal is latched by a test strobe latch and strobed by a flip-flop for use as a control register enable signal.