Abstract: A vertical device geometry for a carbon-nanotube-based field effect transistor has one or multiple carbon nanotubes formed in a trench.

Abstract: A technique of the invention reduces significantly the distance between the gate and single-walled carbon nanotubes to improve performance and efficiency of a carbon nanotube transistor device. Without using a porous template structure, single-walled carbon nanotubes are grown perpendicularly to a substrate between a base metal layer and a middle mesh layer. The nanotubes are insulated with a thin insulator and then gate regions are formed.

Abstract: Fabricating single-walled carbon nanotube transistor devices includes removing undesirable types of nanotubes. These undesirable types of nanotubes may include nonsemiconducting nanotubes, multiwalled nanotubes, and others. The undesirable nanotubes may be removed electrically using voltage or current, or a combination of these. This approach to removing undesirable nanotubes is sometimes referred to as “burn-off.” The undesirable nanotubes may be removed chemically or using radiation. The undesirable nanotubes of an integrated circuit may be removed in sections or one transistor (or a group of transistors) at a time in order to reduce the electrical current used or prevent damage to the integrated circuit during burn-off.

Abstract: A vertical device geometry for a carbon-nanotube-based field effect transistor has one or multiple carbon nanotubes formed in a trench.

Abstract: Techniques are used to fabricate carbon nanotube devices. These techniques improve the selective removal of undesirable nanotubes such as metallic carbon nanotubes while leaving desirable nanotubes such as semiconducting carbon nanotubes. In a first technique, slot patterning is used to slice or break carbon nanotubes have a greater length than desired. By altering the width and spacing of the slotting, nanotubes have a certain length or greater can be removed. Once the lengths of nanotubes are confined to a certain or expected range, the electrical breakdown approach of removing nanotubes is more effective. In a second technique, a Schottky barrier is created at one electrode (e.g., drain or source). This Schottky barrier helps prevent the inadvertent removal the desirable nanotubes when using the electrical breakdown approach. The first and second techniques can be used individually or in combination with each other.

Abstract: Fabricating single-walled carbon nanotube transistor devices includes removing undesirable types of nanotubes. These undesirable types of nanotubes may include nonsemiconducting nanotubes, multiwalled nanotubes, and others. The undesirable nanotubes may be removed electrically using voltage or current, or a combination of these. This approach to removing undesirable nanotubes is sometimes referred to as “burn-off.” The undesirable nanotubes may be removed chemically or using radiation. The undesirable nanotubes of an integrated circuit may be removed in sections or one transistor (or a group of transistors) at a time in order to reduce the electrical current used or prevent damage to the integrated circuit during burn-off.

Abstract: Apparatus and method for synthesizing nanostructures in a controlled process. An embodiment of the apparatus comprises a stage or substrate holder that is heated, e.g., resistively, and is the primary source of heating for the substrate for nanostructure synthesis. The substrate and substrate heater are enclosed in a chamber, e.g., a metal chamber, which is ordinarily at a lower temperature than are the substrate and substrate heater during synthesis. Some embodiments of the invention are particularly useful for chemical vapor deposition (CVD), low pressure CVD (LPCVD), metal organic CVD (MOCVD), and general vapor deposition techniques. Some embodiments of the present invention allow for in situ characterization and treatment of the substrate and nanostructures.

Abstract: Single-walled carbon nanotube transistor devices, and associated methods of making such devices include a porous structure for the single-walled carbon nanotubes. The porous structure may be anodized aluminum oxide or another material. Electrodes for source and drain of a transistor are provided at opposite ends of the single-walled carbon nanotube devices. A concentric gate surrounds at least a portion of a nanotube in a pore. A transistor of the invention may be especially suited for power transistor or power amplifier applications.

Abstract: Single-walled carbon nanotube transistor devices, and associated methods of making such devices include a porous structure for the single-walled carbon nanotubes. The porous structure may be anodized aluminum oxide or another material. Electrodes for source and drain of a transistor are provided at opposite ends of the single-walled carbon nanotube devices. A concentric gate surrounds at least a portion of a nanotube in a pore. A transistor of the invention may be especially suited for power transistor or power amplifier applications.

Abstract: During fabrication of single-walled carbon nanotube transistor devices, a porous template with numerous parallel pores is used to hold the single-walled carbon nanotubes. The porous template or porous structure may be anodized aluminum oxide or another material. A gate region may be provided one end or both ends of the porous structure. The gate electrode may be formed and extend into the porous structure.

Abstract: During fabrication of single-walled carbon nanotube transistor devices, a porous template with numerous parallel pores is used to hold the single-walled carbon nanotubes. The porous template or porous structure may be anodized aluminum oxide or another material. A gate region may be provided one end or both ends of the porous structure. The gate electrode may be formed and extend into the porous structure.