Abstract: The multiplier according to the invention comprises N shift registers (RD.sub.O, . . . , RD.sub.N-1) containing the words x.sub.i on B bits, N conditional adders (AdC.sub.O, . . . , AdC.sub.N-1) each adding to the partial sum which they receive a constant coefficient (a.sub.1), conditional on the value of the bit (x.sub.i,j) which they receive from the associated register (RD.sub.1) and an adder accumulator (AdAc). The digital filter using such a multiplier also comprises a parallel word input register.
Type:
Grant
Filed:
January 24, 1989
Date of Patent:
November 27, 1990
Assignee:
Etat Francais Represente par le Ministere des Postes, des Telecommunication et de L'Espace (CNET)
Inventors:
Pierre Duhamel, Zhijian Mou, Michel Cand
Abstract: A recursive type adder for calculating the sum of two operands. It is used to calculate the sum of two binary data numbers using adders in the form of integrated circuits, particularly for information processing systems wherein the adders constitute one of the fundamental operations of data processing. The invention is classified in the category of parallel-parallel type adders.
Type:
Grant
Filed:
March 7, 1989
Date of Patent:
July 17, 1990
Assignee:
Etat Francais represente par le Ministere des Postes, des Telecommunications et de l'Espace (CNET)