Abstract: A binary multiplier circuit has a logic operator acting as an exclusive-OR gate generating a first intermediate signal which is an exclusive-OR of a first input and a carry-in input. An inverter generates a second intermediate signal. A second logic operator generates a first output bit which is a symmetrical exclusive-OR of a second input and both the first and second intermediate signals. A second output bit is a symmetrical trigger function of the first and second input, depending on the first and second intermediate signals, and is generated in a transmission gate. Since the carry-in signal passed via the first and second intermediate signals is applied directly to transistors of the transmission gate, carry propagation delay is reduced. A fixed operand is multiplied by a variable operand by storing a partial result of the multiplication using an accumulator and a shift register with the binary calculation circuit.

Abstract: A binary calculation circuit has a logic operator acting as an exclusive-OR gate generating a first intermediate signal which is an exclusive-OR of a first input and a carry-in input. An inverter generates a second intermediate signal. A second logic operator generates a first output bit which is a symmetrical exclusive-OR of a second input and both the first and second intermediate signals. A second output bit is a symmetrical trigger function of the first and second input, depending on the first and second intermediate signals, and is generated in a transmission gate. Since the carry-in signal passed via the first and second intermediate signals is applied directly to transistors of the transmission gate, carry propagation delay is reduced.

Abstract: A circuit for performing binary calculation, the circuit being of the type having at least one cell possessing: a first bit input (Ai), a second bit input (Bi), a carry-in input (Ri-1), circuitry (1600) for generating a two input bit exclusive-OR signal (Ai.sym.Bi) and its complement (Ai.sym.Bi), circuitry (1800) for producing a result signal, and circuitry (1900) for producing a carry-out signal (Ri), the circuitry being constituted by multiplexed logic. The complemented two input bit exclusive-OR signal (Ai.sym.Bi) is produced by inverting the two input bit exclusive-OR signal (Ai.sym.Bi), thereby making it possible to utilize only 15 transistors in the most cut-down version of the circuit. The invention also relates to a circuit (20) having an addition cell (22) calculating the sum of the input bits and a subtraction cell (24) calculating the difference of the input bits. The circuitry (1600) for producing the two input bit exclusive-OR signal (Ai.sym.Bi) and its complement (Ai.sym.

Abstract: This filter circuit comprises at least one basic cell (2) arranged as a switched capacitor sampling filter, together with a clock suitable for defining two different states for controlling sampling. According to the main characteristic of the invention, the circuit includes upstream switching means (4) suitable for inverting the polarity of the signal input to the cell during one of the two states, and downstream switching means (6) suitable for inverting the output signal from the cell (2). This makes it possible to transpose the filtering frequency band of the cell (2). The circuit is applicable to manufacturing switched capacitor sampling filters in the form of integrated circuits.

Abstract: With interlaced field scanned TV, a point (P) in a field at time (t+1) is determined on the basis of points situated in said field on the same vertical (C and D), and from points situated in the fields which are adjacent in time (t and t+2). The invention provides for multi-gradient motion detection, i.e. relating not only to the points on the same vertical (C and D), and to the points (A and B) having the same position as the point (P) but in the adjacent fields, but also on the basis of points (E, F, G, and H) which are vertically adjacent to the points (A and B) in the adjacent fields and occupying the same fields. Pairs of such points on either side of the point (P) can thus be defined. Interpolation is performed along each of the available pairs, and the interpolations are weighted as a function of the corresponding gradient.