Abstract: A device embodying the invention for a packet time-division switcher comprises essentially a circuit for detecting beginnings and ends of load interruption periods in the switcher, and a period counter. The detecting circuit is connected to a plurality of input buffer quenes of the switcher and detects a load interruption when all queues signal a state of packet emptiness. A time base of the switcher is inhibited at the end of a period of predetermined duration established by the counter and following the detection of a load interruption. Said duration is predetermined so as to complete the switching of a packet that has been begun. Once the time base is inhibited, the operating of the switcher is interrupted and its power consumption becomes very low. The time base is freed as soon as a packet is received by the queues, and the switcher resumes operating.