Patents Assigned to Eudyna Devices Inc.
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Publication number: 20060214270Abstract: A semiconductor device includes an operating layer made of a semiconductor and a silicon nitride film formed on the operating layer with the use of a mixed gas that includes mono-silane gas, hydrogen gas, and nitrogen gas, by a plasma CVD apparatus, under a condition that a flow rate of the hydrogen gas is 0.2 percent to 5 percent to an overall flow rate.Type: ApplicationFiled: March 27, 2006Publication date: September 28, 2006Applicant: EUDYNA DEVICES INC.Inventor: Norikazu Iwagami
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Publication number: 20060214188Abstract: A semiconductor device includes, an AlGaN electron supply layer having a [000-1] crystalline orientation in a thickness direction to a substrate plane, a GaN electron traveling layer formed on the AlGaN electron supply layer, a gate electrode formed above the GaN electron traveling layer, and a source electrode and a drain electrode between which the gate electrode is located, the source and drain electrode being formed on the GaN electron traveling layer.Type: ApplicationFiled: March 22, 2006Publication date: September 28, 2006Applicant: EUDYNA DEVICES INC.Inventors: Takeshi Kawasaki, Ken Nakata, Hiroshi Yano
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Publication number: 20060193568Abstract: An optical device includes: a first optical component that has an end face oblique with respect to a plane perpendicular to an optical axis; a second optical component that is optically coupled to the first optical component; and a lens that is placed between the first optical component and the second optical component, and is positioned so that the trajectory of a focal point formed when the first optical component and the second optical component rotate relative to each other falls within a valid region on the surface of the second optical component.Type: ApplicationFiled: February 28, 2006Publication date: August 31, 2006Applicant: EUDYNA DEVICES INC.Inventors: Makoto Ito, Sosaku Sawada
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Publication number: 20060177953Abstract: A method of fabricating a semiconductor device includes the steps of forming a step region having a mesa shape in a direction of <011> or <0-11> on a (100) plane of an InP-based compound semiconductor crystal, and burying the step region with InP-based buried layers grown by vapor-phase growth by supplying a base gas to which a chlorinated organic compound is added, the organic chlorine compound including at least two carbon atoms, and each of the carbon atoms is bonded to one chlorine (Cl) atom in one molecule. The chlorinated organic compound is any one of 1,2-dichloroethane, 1,2-dichloropropane, and 1,2-dichloroethylene.Type: ApplicationFiled: February 8, 2005Publication date: August 10, 2006Applicant: EUDYNA DEVICES INC.Inventor: Tatsuya Takeuchi
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Patent number: 7087957Abstract: A semiconductor device includes a compound semiconductor substrate, a channel layer provided on the compound semiconductor substrate, a buried layer provided on the channel layer, a first recess formed in the buried layer in an E-mode region, a second recess formed in the first recess in the E-mode region and another second recess formed in the buried layer in a D-mode region, and a gate electrode provided in the second recess in the E-mode region and another gate electrode provided in the second recess in the D-mode region, and a distance between a surface of the buried layer and a bottom of the second recess in the E-mode region is shorter than another distance between another surface of the buried layer and a bottom of said another second recess in the D-mode region.Type: GrantFiled: January 14, 2005Date of Patent: August 8, 2006Assignee: Eudyna Devices, Inc.Inventor: Hajime Matsuda
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Patent number: 7088201Abstract: A broadside 90° microwave coupler is composed of three metal layers in a homogeneous dielectric media. The coupler is constructed in a multi-layer configuration with two conductor strips arranged on top of each other so as to be electro-magnetically coupled. A ground plane formed with a third metal layer below the coupled conductor strips is opened so that it is separated from the conductor strips by a gap. The two conductor strips are fully embedded into the dielectric layer. The characteristic physical dimensions of the coupler are determined to achieve the desired coupling coefficient while maintaining low reflection, high isolation and phase balance at the output ports of the coupler.Type: GrantFiled: August 4, 2004Date of Patent: August 8, 2006Assignee: Eudyna Devices Inc.Inventor: Belinda Piernas
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Publication number: 20060157735Abstract: At a gate electrode formed on a compound semiconductor layer with a Schottky junction, a diffusion preventing layer made of TixW1?xN (0<x<1) for suppressing the metal of a low-resistance metal layer from diffusing to the compound semiconductor layer is provided between a Ni layer forming a Schottky barrier with the compound semiconductor layer and the low-resistance metal layer, and thus an increase in the leak current at the gate electrode is suppressed.Type: ApplicationFiled: December 7, 2005Publication date: July 20, 2006Applicants: FUJITSU LIMITED, EUDYNA DEVICES INC.Inventors: Masahito Kanamura, Masahiro Nishi
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Publication number: 20060108660Abstract: An amplifier circuit includes an amplifier having an amplifying device composed of GaN or a GaN compound semiconductor used for an active region, and a distortion compensation circuit that is connected to the amplifier, has an attenuation characteristic, and has a negative phase distortion.Type: ApplicationFiled: November 15, 2005Publication date: May 25, 2006Applicant: EUDYNA DEVICES INC.Inventor: Norihiko Ui
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Publication number: 20060035683Abstract: A semiconductor device includes a decoder decoding input signals and generating a control signal from decoded input signals, and a power control circuit detecting a given combination of the input signals applied to the decoder and controlling a supply of power to the decoder.Type: ApplicationFiled: August 10, 2005Publication date: February 16, 2006Applicant: EUDYNA DEVICES INC.Inventor: Naoyuki Miyazawa
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Patent number: 6998695Abstract: A method of manufacturing a semiconductor device has the steps of: forming a mushroom gate traversing an active region of a semiconductor substrate and having a fine gate and an expanded over gate formed thereon; coating a first organic material film on the semiconductor substrate; patterning the first organic material film and leaving the first organic material film only near the mushroom gate; coating a second organic (insulating) material film covering the left first organic material film; forming an opening through the second organic material film to expose the first organic material film; and dissolving and removing the first organic material film via the opening to form a hollow space in the second organic material film.Type: GrantFiled: August 28, 2003Date of Patent: February 14, 2006Assignees: Fujitsu Limited, Eudyna Devices Inc.Inventors: Kozo Makiyama, Tsuyoshi Takahashi, Masahiro Nishi
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Publication number: 20060028704Abstract: An electronic module includes: a first-stage circuit producing a drive signal based on a first potential that is either a positive or negative potential; a second-stage circuit including a first element reversely driven between a second potential equal to the first potential and the drive signal, and a second element connected in a forward biasing direction toward the second potential; and a transmission line having a signal conductor over which the drive signal is transmitted to the first element, and a reference conductor maintained at a reference potential. A connection between the first potential of the first-stage circuit and the reference conductor of the transmission line and a connection between the second potential of the second-stage circuit and the reference conductor are at an equal potential.Type: ApplicationFiled: June 23, 2005Publication date: February 9, 2006Applicant: EUDYNA DEVICES INC.Inventors: Shingo Inoue, Ken Ashizawa
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Publication number: 20050274877Abstract: An optical module includes a light-emitting element, a light-receiving element, and a reflector. The light-emitting element and the light-receiving element are mounted in the optical module, and the reflector composed of a wire or a ribbon reflects and guides an emitted light to a light-receiving surface.Type: ApplicationFiled: June 9, 2005Publication date: December 15, 2005Applicant: EUDYNA DEVICES INC.Inventor: Kazuyoshi Watanabe
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Publication number: 20050253671Abstract: A filter includes first and second line patterns each having a length substantially equal to ½ of the wavelength of a pass-band frequency, and a resonator that is interposed between the first and second line patterns and is coupled therewith so that the first and second line patterns have open stubs in which connection points between input/output terminals and the first and second line patterns appear to be short-circuited when viewed from ends of the first and second line patterns.Type: ApplicationFiled: October 7, 2004Publication date: November 17, 2005Applicant: EUDYNA DEVICES INC.Inventors: Tomoko Hamada, Hiroshi Nakano
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Publication number: 20050250336Abstract: A method of fabricating a semiconductor device includes forming a film stack having a Ti film and a metal film containing Ni sequentially deposited on a surface of a substrate of a GaN based semiconductor, SiC, or sapphire, patterning the film stack to expose a portion of the surface of the etching substance, and dry etching an exposed portion of the surface of the etching substance. It is thus possible to enhance the adhesion between a dry etching mask and the surface of the etching substance. Peeling and cracking are suppressed and the highly accurate etching can be performed.Type: ApplicationFiled: May 10, 2005Publication date: November 10, 2005Applicant: EUDYNA DEVICES INC.Inventor: Tsutomu Komatani
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Publication number: 20050236365Abstract: A method of dry etching an etching layer that coats a surface of a GaN based semiconductor layer or a SiC, the method includes performing a first plasma etching to remain a desired thickness of the etching layer, and performing a second plasma etching on a region remained by the first plasma etching with a lower energy than that of the first plasma etching to expose a surface of the GaN based semiconductor layer or the SiC. The method of dry etching of the present invention is capable of suppressing the damage on the GaN based semiconductor layer and thereby achieving the dry etching method of the high selectivity, high anisotropy, low contamination, and low damage. It is thus possible to achieve the GaN based semiconductor device having excellent initial device characteristics and free from degradation due to conduction.Type: ApplicationFiled: April 27, 2005Publication date: October 27, 2005Applicant: EUDYNA DEVICES, INC.Inventor: Tsutomu Komatani
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Publication number: 20050230765Abstract: A semiconductor device includes: a semiconductor substrate having a source region and a drain region; and an offset region that is provided in the semiconductor substrate and extends from an edge of a gate electrode toward the drain region. The offset region includes multiple regions having different impurity concentrations formed by an ion implantation with a mask having an opening ratio that changes from the gate electrode to the drain region and by subsequent thermal treatment. The multiple regions include a concentration gradient region that is interposed between adjacent ones of the multiple regions and has the impurity concentration that gradually changes.Type: ApplicationFiled: March 30, 2005Publication date: October 20, 2005Applicant: EUDYNA DEVICES INC.Inventor: Fumio Ohtake
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Publication number: 20050221786Abstract: A radio communication device includes: a local oscillator; an amplifier amplifying an output signal of the local oscillator and outputting a local oscillation frequency and a harmonic wave component thereof; and a harmonic mixer receiving an output signal of the amplifier and an information signal, and generating an up-converted signal of the information signal with the harmonic wave component based on the local oscillation frequency, while allowing the harmonic wave component to pass through.Type: ApplicationFiled: March 31, 2005Publication date: October 6, 2005Applicant: EUDYNA DEVICES INC.Inventors: Hiroshi Nakano, Yasutake Hirachi
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Publication number: 20050221628Abstract: A semiconductor device includes a silicon nitride (SiN) film provided on a crystal surface of a nitride semiconductor, the SiN film having a hydrogen content equal to or smaller than 15 percent.Type: ApplicationFiled: March 30, 2005Publication date: October 6, 2005Applicant: EUDYNA DEVICES INC.Inventors: Masahiro Tanaka, Tsutomu Komatani
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Publication number: 20050221772Abstract: A harmonic mixer comprising an anti-parallel diode having two diodes connected in parallel in reverse directions between first and second ends, the first end receiving a local oscillation signal, and the second end receiving an information signal and a DC bias, an output signal of the harmonic mixer being available at the second end. With the capabilities of the anti-parallel diode, it is possible to realize the radio communication with the use of a high frequency range at least 30 GHz at a low cost and with a simple configuration of the harmonic mixer and the radio communication device having the same, although it is considered hard to generate the stable local oscillation frequency for the radio communication of at least 30 GHz.Type: ApplicationFiled: March 31, 2005Publication date: October 6, 2005Applicant: EUDYNA DEVICES INC.Inventors: Hiroshi Nakano, Yasutake Hirachi
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Publication number: 20050189584Abstract: A semiconductor device includes a compound semiconductor substrate, a channel layer provided on the compound semiconductor substrate, a buried layer provided on the channel layer, a first recess formed in the buried layer in an E-mode region, a second recess formed in the first recess in the E-mode region and another second recess formed in the buried layer in a D-mode region, and a gate electrode provided in the second recess in the E-mode region and another gate electrode provided in the second recess in the D-mode region, and a distance between a surface of the buried layer and a bottom of the second recess in the E-mode region is shorter than another distance between another surface of the buried layer and a bottom of said another second recess in the D-mode region.Type: ApplicationFiled: January 14, 2005Publication date: September 1, 2005Applicant: EUDYNA DEVICES INC.Inventor: Hajime Matsuda