Abstract: A process, and structure, used to monitor and control the level of photoresist removed at the periphery of a photoresist coated, semiconductor substrate, has been developed. A monitoring structure comprised of a group of graduated scribe marks, laser formed near the periphery of the semiconductor, monitoring substrate, is included with product semiconductor substrates, during the application of a photoresist layer, and during the photoresist edge bead removal procedure. The width of the photoresist edge bead, removed from product semiconductor substrates is determined via examination of the monitoring semiconductor substrate, in terms of measuring the level of graduated scribe marks, now exposed. This measurement determines the status of the product semiconductor substrates, in regards to continued processing, or rework.

Abstract: LCDs for use in high intensity applications such as digital projectors are susceptible to performance degradation resulting from unwanted photoconductive effects that result from scattered light. Furthermore, the constraints under which these devices operate require that their TFTs be made of polysilicon. The present inventions shows how these problems can be overcome by inserting an opaque optical shielding element between the TFT active layer and the lower transparent plate of the LCD. Materials suitable for use in the shielding layer include thermally deposited silicon nitride, layers of silicon oxide and silicon nitride, and a refractory metal encapsulated in a suitable barrier layer.

Abstract: A process for integrating the fabrication of an N type, junction field effect transistor (NJFET), device, with the fabrication and a high voltage, P channel metal oxide semiconductor (PMOS), device, has been developed. The process includes the formation of a deep N well region for accommodation of the high voltage, PMOS device, while a shallow N well region is used to contain the NJFET device. Featured in the integrated fabrication sequence is the simultaneous formation of P type source/drain regions for the high voltage PMOS device, and the P type gate structure of the NJFET device.