Patents Assigned to Evalue Technology Inc.
  • Patent number: 7526584
    Abstract: A method for setting up a serial communication port configuration is disclosed. The method comprises a hardware circuit of a motherboard having a plurality of digital logic gates and a plurality of chips disposed thereon, wherein a process is initiated when the digital logic gates receive a high or low electric potential signal inputted by a general programmable input/output (GPIO), and the processed high or low electric potential signal is transmitted to the chips for further processing and outputting the same to execute setting up of the serial communication port configuration.
    Type: Grant
    Filed: September 26, 2006
    Date of Patent: April 28, 2009
    Assignee: Evalue Technology Inc.
    Inventors: Cheng-Ping Yu, Hung-Chi Lin
  • Patent number: 7512775
    Abstract: A method for initializing and actuating a peripheral by a mainframe with initialization and actuation codes of the periphery stored in a memory comprises the steps of: detecting a peripheral being connected to the mainframe; detecting a type number of the peripheral; the CPU loading initial codes and actuation codes about the type number from the memory of the main frame; sending reset signals to peripheral to reset the peripheral; initializing and actuating the peripherals; sending the initialization and actuating process; and mainframe retaining to be connected to the peripheral. If it is detected that a peripheral is connected to the main frame, while the initialization and actuation codes in the memory of the main frame, the CPU loads the initialization and actuation codes from a memory of a peripheral and then the process enter to the sending step. The device for performing the method is also included.
    Type: Grant
    Filed: February 6, 2006
    Date of Patent: March 31, 2009
    Assignee: Evalue Technology Inc.
    Inventor: Feng-Yun Lin
  • Publication number: 20080122480
    Abstract: A method for setting up a serial communication port configuration is disclosed. The method comprises a hardware circuit of a motherboard having a plurality of digital logic gates and a plurality of chips disposed thereon, wherein a process is initiated when the digital logic gates receive a high or low electric potential signal inputted by a general programmable input/output (GPIO), and the processed high or low electric potential signal is transmitted to the chips for further processing and outputting the same to execute setting up of the serial communication port configuration.
    Type: Application
    Filed: September 26, 2006
    Publication date: May 29, 2008
    Applicant: EVALUE TECHNOLOGY INC.
    Inventors: Cheng-Ping Yu, Hung-Chi Lin
  • Publication number: 20080091959
    Abstract: An auto management for a power system is disclosed. The power system disposed on a motherboard. The motherboard comprises a microcomputer controller, a first low power consumption module and a second low power consumption module. The microcomputer controller disposed on the motherboard is adopted for outputting a power control signal to the first low power consumption module or the second low power consumption module and inputting the power control signal to a main system from the first low power consumption module or a sub-system from the second low power consumption module when the microcomputer controller senses a signal of an external power supply.
    Type: Application
    Filed: October 12, 2006
    Publication date: April 17, 2008
    Applicant: EVALUE TECHNOLOGY INC.
    Inventors: Cheng-Ping Yu, Hung-Chi Lin