Abstract: A scalable system for verifying electronic circuit designs in anticipation of fabrication by compiling a hardware description to instructions for canvassing processors and instructions for circuit evaluation processors which are scalably interconnected to provide simulation and emulation, having deterministically scheduled transfer of circuit signal values among the large number of circuit evaluation processors.
Type:
Grant
Filed:
January 26, 2006
Date of Patent:
June 16, 2009
Assignee:
Eve S.A.
Inventors:
Subbu Ganesan, Leonid Alexander Broukhis, Ramesh Narayanaswamy, Ian Michael Nixon, Thomas Hanni Spencer
Abstract: A logic simulation acceleration processor optimized for multi-value logic level simulation of electronic systems described in hardware description languages.
Type:
Grant
Filed:
January 25, 2006
Date of Patent:
March 24, 2009
Assignee:
Eve S.A.
Inventors:
Subbu Ganesan, Leonid Alexander Broukhis, Ramesh Narayanaswamy, Ian Michael Nixon, Thomas Hanni Spencer