Abstract: Once a delay locked loop has been locked to a clock signal, an omitted clock cycle is injected into the input of the delay locked loop without stopping the operation of the delay locked loop. The omitted cycle is later detected at an output of the delay locked loop, and the delay between the input and output is determined based on the time the omitted cycle requires to propagate through the delay locked loop. Once determined, the number of cycles of delay for the delay locked loop can be used in conjunction with an internal clock signal to launch data and/or data strobes from memory devices and memory controllers such that the proper phase alignment and clock cycle alignment is achieved.

Abstract: Higher word line voltages facilitate write operations in spin-torque magnetic memory devices, but overdriving the gate of a selection transistor with such higher word line voltages can damage the selection transistor if the gate-to-source voltage for the selection transistor is too high. Therefore in order to support the word line voltage needed on the gate of the select transistor for an up-current write operation without exceeding limits on the gate-to-source voltage for the select transistor, the gate of the selection transistor can be driven in a two-step process. The gate of the selection transistor is first driven to a lower voltage within the limits of the gate-to-source voltage for the transistor when the source of the transistor is grounded or at a voltage near ground. A voltage is then applied across the memory cell, which results in the source of the selection transistor being raised above its initial ground or near-ground state.

Abstract: In some examples, a memory device is configured with a reduced command set and a variable burst length. In some instances, the variable burst length defines a page size associated with data to be loaded into a cache. In other instances, the variable burst length may be set on the fly per read/write command and, in some cases, the burst length may be utilized to define the page size associated with the read/write command.

Abstract: A method is provided for healing reset errors for a magnetic memory using destructive read with selective write-back, including for example, a self-referenced read of spin-torque bits in an MRAM. Memory cells are prepared for write back by one of identifying memory cells determined in error using an error correcting code and inverting the inversion bit for those memory cells determined in error identifying memory cells determined in error using an error correcting code and resetting a portion of the memory cells to the first state; and resetting one or more memory cells to the first state.

Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes. For example, an exemplary method of manufacturing a magnetoresistive device includes etching through a second electrode, second dielectric layer and free magnetic layer to provide a sidewall of (i) an unpinned synthetic antiferromagnetic structure, (ii) a second dielectric layer and (iii) a free magnetic layer; thereafter, forming an encapsulation material on the sidewall of the unpinned synthetic antiferromagnetic structure, second dielectric layer and free magnetic layer, and after forming the encapsulation material, etching through a first dielectric layer.

Abstract: A magnetic field sensor that includes a differential bridge in which each path of the bridge includes a first type of magnetic field sensing device and a second type of magnetic field sensing device. The first and second types of magnetic field sensing devices differ in the magnetic moment imbalance present in the synthetic antiferromagnets (SAFs) included in their reference layers such that that different types of devices produce a different response to perpendicular magnetic fields, but the same response to in-plane magnetic fields. Such different magnetic moment imbalances in the SAFs of magnetic field sensing devices included in a bridge allow for accurate sensing of perpendicular magnetic fields in a differential manner that also cancels out interference from in-plane fields. Techniques for producing such magnetic field sensing devices on an integrated circuit are also presented.

Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes (a) etching through at least a portion of a thickness of the surface region to create a first set of exposed areas in the form of multiple strips extending in a first direction, and (b) etching through at least a portion of a thickness of the surface region to create a second set of exposed areas in the form of multiple strips extending in a second direction. The first set of exposed areas and the second set of exposed areas may have multiple areas that overlap. The method may also include, (c) after the etching in (a) and (b), etching through at least a portion of the thickness of the magnetoresistive stack through the first set and second set of exposed areas.

Abstract: An integrated circuit package may comprise a multilayer frame package including: a bottom layer; and a magnetic shield layer, including a sub-frame and a magnetic shield disposed within a periphery of the sub-frame; and an integrated circuit die provided on or above the magnetic shield layer of the multilayer frame package.

Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.

Abstract: A magnetoresistive element (e.g., a spin-torque magnetoresistive memory element) includes a fixed magnetic layer, a free magnetic layer, having a high-iron alloy interface region located along a surface of the free magnetic layer, wherein the high-iron alloy interface region has at least 50% iron by atomic composition, and a first dielectric, disposed between the fixed magnetic layer and the free magnetic layer. The magnetoresistive element further includes a second dielectric, having a first surface that is in contact with the surface of the free magnetic layer, and an electrode, disposed between the second dielectric and a conductor. The electrode includes: (i) a non-ferromagnetic portion having a surface that is in contact with a second surface of the second dielectric, and (ii) a second portion having at least one ferromagnetic material disposed between the non-ferromagnetic portion of the electrode and the conductor.

Abstract: In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.

Abstract: A magnetoresistive magnetic tunnel junction (MTJ) stack includes a free magnetic region, a fixed magnetic region, and a dielectric layer positioned between the free magnetic region and the fixed magnetic region. In one aspect, the fixed magnetic region consists essentially of an unpinned, fixed synthetic anti-ferromagnetic (SAF) structure which comprises (i) a first layer of one or more ferromagnetic materials, including cobalt, (ii) a multi-layer region including a plurality of layers of ferromagnetic materials, wherein the plurality of layers of ferromagnetic materials include a layer of one or more ferromagnetic materials including cobalt, and (iii) an anti-ferromagnetic coupling layer disposed between the first layer and the multi-layer region. The free magnetic region may include a circular shape, the one or more ferromagnetic materials of the first layer may include cobalt, iron and boron, and the dielectric layer may be disposed on the first layer.

Abstract: A magnetoresistive device comprises a fixed magnetic region positioned on or over a first electrically conductive region, an intermediate layer positioned on or over the fixed magnetic region, a free magnetic region positioned on or over the intermediate layer, and a metal insertion substance positioned in contact with the free magnetic region, wherein the metal insertion substance includes one or more transition metal elements.

Abstract: A magnetic field sensor includes a plurality of transducer legs coupled together as a first circuit to sense a magnetic field, wherein each transducer leg comprises a plurality of magnetoresistance sense elements. The magnetic field sensor also includes a second circuit including a first plurality of current lines, wherein each current line of the first plurality of current lines is adjacent to a corresponding plurality of magnetoresistance sense elements of a transducer leg of the plurality of transducer legs. When at least one current line of the first plurality of current lines is energized, a magnetization of each magnetoresistance sense element of the transducer leg is aligned in a first direction or a second direction opposite to the first direction. A routing pattern of the at least one current line is configured to generate an equal population of magnetoresistance sense elements with magnetization aligned in the first and second directions.

Abstract: A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer, (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.

Abstract: A method of manufacturing one or more interconnects to a magnetoresistive structure, the method comprising depositing a first conductive material (i) in a via which is formed through a first surface of a first dielectric layer and (ii) directly on the first surface of the first dielectric layer. The method further includes etching the first conductive material wherein, after etching the first conductive material, a portion of the first conductive material remains (i) in the via and (ii) directly on the first surface of the first dielectric layer. The method also includes partially filling the via by depositing a second conductive material (i) in the via and (ii) directly on the first conductive material remaining in the via, depositing a first electrode material (i) in the via and (ii) directly on the second conductive material which is in the via, and forming a magnetoresistive structure over the first electrode material.

Abstract: The present disclosure is drawn to, among other things, a method of forming a semiconductor shield from a stock material having a thickness. In some aspects the methods includes providing a first layer of material on a first surface of the stock material, wherein at least a portion of the first layer of material includes a first window that exposes a portion of the first surface; providing a second layer of material on a second surface of the stock material, wherein the second surface of the stock material is spaced from the first surface by the thickness of the stock material, and wherein at least portion of the second layer of material includes a second window that exposes a portion of the second surface; and selectively removing a portion of the stock material exposed at the first or second windows, wherein the portion removed includes less than an entirety of the thickness of the stock material.

Abstract: Once a delay locked loop has been locked to a clock signal, an omitted clock cycle is injected into the input of the delay locked loop without stopping the operation of the delay locked loop. The omitted cycle is later detected at an output of the delay locked loop, and the delay between the input and output is determined based on the time the omitted cycle requires to propagate through the delay locked loop. Once determined, the number of cycles of delay for the delay locked loop can be used in conjunction with an internal clock signal to launch data and/or data strobes from memory devices and memory controllers such that the proper phase alignment and clock cycle alignment is achieved.

Abstract: The present disclosure is drawn to, among other things, a method of managing a memory device. In some aspects, the method includes receiving data to be stored in a storage memory, wherein the storage memory is coupled to the memory device, wherein the memory device includes a first memory type and a second memory type different from the first memory type; storing a first copy of the received data in the first memory type; storing a second copy of the received data in the second memory type; receiving indication of a power loss to the memory device; in response to receiving indication of the power loss, copying the second copy from the second memory type to the storage memory; detecting for power restoration to the memory device after the power loss; and in response to detecting power restoration to the memory device, restoring data to the first memory type by copying data from the second memory type to the first memory type.

Abstract: A method is provided for healing reset errors for a magnetic memory using destructive read with selective write-back, including for example, a self-referenced read of spin-torque bits in an MRAM. Memory cells are prepared for write back by one of identifying memory cells determined in error using an error correcting code and inverting the inversion bit for those memory cells determined in error; identifying memory cells determined in error using an error correcting code and resetting a portion of the memory cells to the first state; and resetting one or more memory cells to the first state.