Abstract: The invention concerns a method of manufacturing an assembly of electronic components on a front surface of a semiconductor substrate comprising a plurality of field areas, each field area comprising at least one field and each field comprising at least one electronic component, the method comprising a plurality of photolithography steps to form a stack of layers forming each electronic component, each photolithography step defining a mask level and comprising the application of a mask successively on each field in photolithography equipment, the positioning of said mask on each field being performed relative to a reference mask level, one of the masks being designated as identification mask.

Abstract: The invention concerns a method of manufacturing an assembly of electronic components (3) on the front surface of a semiconductor wafer (1) comprising a plurality of field areas (4), each area (4) comprising at least one field (2) and each field (2) comprising at least one electronic component (3). The method comprises a plurality of photolithography steps to form a stack of layers forming each electronic component (3), each photolithography step comprises the application of a mask successively on each field (2) in photolithography equipment. One of the masks further comprises an identification pattern, said mask being called identification mask. At the photolithography step associated with the identification mask, as least one photolithographic parameter of the photolithography equipment is different for each field area (4), to expose the identification pattern differently in each field area (4).

Abstract: The invention concerns a field-effect transistor (100) having an interdigited structure and comprising: a plurality of elementary transistor cells (50) arranged in parallel, each elementary cell comprising a source electrode (1), a drain electrode (3), and a gate electrode (2) interposed between the source and drain electrodes, a source terminal (10) and a drain terminal (30) respectively connected to the source electrodes (1) and to the drain electrodes (3) of the elementary cells (50), a gate terminal (20) connected to the gate electrodes (2) of the elementary cells. The field-effect transistor (100) only comprises vertical conductive vias to connect the gate electrodes to the gate terminal, and the gate terminal (20) is arranged vertically in line with all or part of the elementary cells (50).

Abstract: The disclosure concerns an electronic device comprising, stacked from a first surface to a second surface, a first stack and a second stack of two high electron mobility transistors, referred to as first and second transistor, the first and the second stack each comprising, from an insulating layer, interposed between the first and the second stack, a barrier layer and a channel layer, the first and the second transistor respectively comprising a first and a second set of electrodes, the first and the second set of electrodes being each provided with a source electrode, with a drain electrode, and with a gate electrode which are arranged so that the first and the second transistor form a half-arm of a bridge.

Abstract: The disclosure concerns a device which comprises a stack of two high electron mobility transistors, referred to as first and second transistor, separated by an insulating layer and each provided with a stack of semiconductor layers respectively referred to as first stack and second stack, the first and the second stack each comprising, from the insulating layer to, respectively, a first and a second surface, a barrier layer and a channel layer, the first and the second transistor respectively comprising a first set of electrodes and a second set of electrodes, the first and the second set of electrodes each comprising a source electrode, a drain electrode, and a gate electrode which are arranged so that the first and the second transistor are electrically connected head-to-tail.

Abstract: The disclosure concerns an electronic device provided with two high electron mobility transistors stacked on each other and having in common their source, drain, and gate electrodes. For example, each of these electrodes extends perpendicularly to the two transistors. For example, the source and drain electrodes electrically contact the conduction channels of each of the transistors so that said channels are electrically connected in parallel.

Abstract: The disclosure concerns an electronic assembly which extends along a stacking direction from a lower surface to an upper surface coupled by an edge surface, the assembly comprises at least two elementary modules stacked along the stacking direction, which each comprise, along the stacking direction and from a back side to a front side, two high electron mobility transistors respectively called back transistor and front transistor, separated by an insulator layer, and having in common a source electrode, a drain electrode, and a gate electrode, the assembly of the front and back transistors being electrically connected in parallel, the electronic assembly comprises, arranged on the front side of each elementary module, a contact layer, electrically contacting the gate electrode of the considered elementary module from its front side, each of the contact layers comprising an electric contact point emerging onto the edge surface.

Abstract: The disclosure concerns an electronic device comprising a HEMT transistor, called main transistor, and at least another HEMT transistor, called additional transistor, stacked on each other. The main transistor and the additional transistor comprise a common drain electrode and, respectively, a main source electrode and an additional source electrode, arranged so that electric conduction paths likely to be formed by the two conduction layers are connected in parallel when one and the other of the HEMT transistors are in the conductive state.