Abstract: As a non-limiting example, various aspects of this disclosure provide embodiments of AC direct drives for light emitting diodes for a wide variety of drive stages.

Abstract: In order to get the best of both high and low common mode ranges, an adaptive body biasing method using a pair of replica devices is implemented. Each replica device corresponds to a NMOS (or PMOS) device that constitutes the input pair used in a logic circuit or other type of integrated circuits. This configuration helps to increase the threshold voltage of the device, utilizing body effect, at high input common mode voltage, as desired for NMOS, and at low input common mode voltage, as desired for PMOS. At the same time, this configuration scales the threshold back to normal at low input common mode voltages, thereby countering the negative impact of body effect. In short, the body bias applied to the NMOS (or PMOS) device helps in adapting the threshold voltage to the operating condition.

Abstract: A system supporting enhanced programmable signal adjustments may include a plurality of circuits configured to generate a corresponding plurality of input signals; a signal conditioner configured to condition the plurality of signals; and a controller configured to control the signal conditioner. The controller may generate one or more control signals for the controlling of the signal conditioner. The signal conditioner may select one or more input signals from the plurality of input signals, based on a first control signal generated by the controller; may generate an adjustment signal based on a second control signal generated by the controller; and may adjust at least one of the selected one or more input signals based on the adjustment signal and a third control signal generated by the controller.

Abstract: As a non-limiting example, various aspects of this disclosure provide embodiments of AC direct drives for light emitting diodes for a wide variety of drive stages.

Abstract: In order to get the best of both high and low common mode ranges, an adaptive body biasing method using a pair of replica devices is implemented. Each replica device corresponds to a NMOS (or PMOS) device that constitutes the input pair used in a logic circuit or other type of integrated circuits. This configuration helps to increase the threshold voltage of the device, utilizing body effect, at high input common mode voltage, as desired for NMOS, and at low input common mode voltage, as desired for PMOS. At the same time, this configuration scales the threshold back to normal at low input common mode voltages, thereby countering the negative impact of body effect. In short, the body bias applied to the NMOS (or PMOS) device helps in adapting the threshold voltage to the operating condition.

Abstract: Enhanced multi-channel sensor interfaces with programmable signal adjustments are provided. An example sensor interface may include an input selector that selects one or more sensor signals from a plurality of sensor signals based on input selection control signal; an offset generator that generates an offset signal based on an offset control signal; and a programmable signal adjuster that adjusts at least one selected sensor signal based on the generated offset signal and a signal adjustment control signal. The sensor interface may include a control interface unit that generates the input selection control signal, the offset control signal, and the signal adjustment control signal. The sensor interface may include a comparator that compares output of the programmable signal adjuster with a reference signal, and provides based on the comparison an output configured for use in performing offset correction. The programmable signal adjuster may generate a number of selectable gains.

Abstract: A clock divider includes, in part, a pair of counters and a programmable delay line. A first one of the counters operates at a first frequency and is configured to count using a first integer portion of the divisor. The second counter operates at a second frequency smaller than the first frequency and is configured to count using a second integer portion of the divisor. The programmable delay line includes, in part, a chain of delay elements configured to generate a multitude of delays of the output of the second counter. A multiplexer selects one of the generated delays in accordance with the fractional portion of the divisor. The second counter increases its count only when the first counter reaches a terminal count. The first and second integer portions are loaded respectively into the first and second counters when the second counter reaches its terminal count.

Abstract: A highly integrated programmable sensor interface with improved sensor signal calibration and conditioning functions is described. The programmable sensor interface according to the present invention sensor interface provides programmable gain, digital offset correction and bias for one or more signal channels on one chip on a per channel basis. According to another aspect of the invention, the sensor interface provides reference voltage and sensor biasing by using an on-chip precision voltage regulator. According to one aspect of the invention, multiple inputs are multiplexed and each is applied to a variable gain instrumentation amplifier, which connects to the output. The offset of a given channel is controlled by an on-chip DAC which has multiple digital storage registers, allowing each channel to have a unique, stored offset. Offsets and gains are programmed externally.

Abstract: The present invention relates to a clock and data recovery (CDR) unit comprising of a bang-bang phase detector to receive data and a recovered clock from a phase selector multiplexer. The phase detector produces a late and an early comparison output. A block (digital filter) receives the late and early input and produces a multiplexer selector control signal. The phase selector multiplexer selects a clock phase as the recovered clock signal using multiplexer selector control signal.

Abstract: Digital logic receives a gapped and jittery clock signal with specified frequency and frequency offset allowed by specification and a reference clock signal with same specified frequency and different frequency offset allowed by specification having low jitter. The digital logic adds and/or removes cycles from the reference clock signal over an extended period of time to produce a produced clock signal with low jitter that has a frequency that approaches the frequency of the gapped and jittery clock signal. The produced clock signal being provided as feedback to the digital frequency comparator and also acts as final dejitter smooth clock output with 50% duty cycle.

Abstract: In described embodiments, processing of a data stream, such as a packet stream or flow, associated with data streaming is improved by context switching that employs context history. For each data stream that is transformed through processing, a context is maintained that comprises state information and includes a history and state information that enables the transformation for the data stream. Processing for the data transformation examines currently arriving data and then processes the data based on the context data and previously known context information for the data stream from the history stored in memory.

Abstract: An Electrostatic Discharge (ESD) protection circuitry comprises a protection device structure. The protection device structure includes at least one transistor with a gate operably connected to a pad. The at least one transistor turns on upon an ESD event and conducting charge to a substrate. At least one additional transistor with a gate operably connected to the substrate turns on after the at least one transistor upon an ESD protection event.

Abstract: The present application relates to boost-resonant converter for driving high brightness LEDs (HB LED) that incorporates power factor correction (PFC) and does not require a bulky electrolytic capacitor. The new converter incorporates the PFC and the LED supplies into a single stage. The system allows a large voltage ripple across the intermediate energy storage capacitor reducing its value. Constant light output and dimming capability are obtained by variable frequency current control of the resonant converter. A high power factor is achieved by DCM boost front-end portion with controlled average output voltage. The converter is regulated by a digital controller that implements a variable-frequency variable duty ratio algorithm. Experimental results with a 15 W prototype verify near unity power factor operation, above 88% efficiency and constant lamp current over the entire operating range.

Abstract: A multiphase controller for a DC-to-DC power supply includes logic to estimate parameters for multiple phases that provide a combined output at a load. The estimated parameters include a current estimate and an effective resistance estimates for each phase so that a power estimate for each phase can be produced. The logic adjusts the operation of the phases using the power estimate for each phase.

Abstract: A digital pulse controller uses digital logic to send pulses to a high side and low side switches of a switch-mode power supply converter. The digital logic uses a pulse frequency mode which includes a frequency targeting mode and an ultrasonic mode. The frequency targeting mode dynamically adjusts the size of the pulses in order to achieve a switching frequency within a desired band. The ultrasonic mode is switched into when the frequency of the pulses are at or below a threshold and the time of the pulses reaches a minimum threshold.

Abstract: The present invention uses a reference voltage that varies within a Pulse Width Modulation (PWM) cycle to generate the PWM signal. This allows for stability in the feedback of Constant On-Time (COT) control for buck controllers when low Equivalent Series Resistance (ESR) capacitors are used as the output capacitor. The reference voltage is adjusted using features of a PWM cycle in a voltage mode without using external inductor current information.

Abstract: An Electrostatic Discharge (ESD) protection circuitry comprises a protection device structure. The protection device structure includes at least one transistor with a gate operably connected to a pad. The at least one transistor turns on upon an ESD event and conducting charge to a substrate. At least one additional transistor with a gate operably connected to the substrate turns on after the at least one transistor upon an ESD protection event.

Abstract: A chip includes a pool of blocks. Each block is adapted to implement a communication protocol. A cross-connect configurably connects between the blocks. A configured connection through the cross-connect between a sending block and a receiving block includes a lane with a toggle line and multiple data lines. The receiving block uses the toggle line to determine when valid data is on the data lines. The sending block and receiving block are on different clock domains.

Abstract: A controller produces high-side and low-side control signals. The high and low-side signals are used to switch high-side and low-side transistors in the power stage to control the voltage across the power stage output capacitor of the power stage. A boost feedback charge pump receives the low or high-side signal to increase the charge on a charge pump output capacitor. The controller is configured to send Pulse Frequency Modulation (PFM) high and low-side signals that control the voltage on the power stage output capacitor and charge the charge pump output capacitor. The controller is also configured to send boost feedback (BFB) high and low-side signals that charge the boost feedback capacitor, but are designed to not significantly change the charge on the power stage output capacitor.

Abstract: A Higher order (HO) Optical channel Data Unit (ODU)k signal is extracted from an HO Optical channel Transport Unit (OTU)k signal using a first clock at or faster than the OTUk clock. An HO Optical channel Payload Unit OPUk signal is extracted from the HO ODUk signal using the first clock. An Optical channel Data Tributary Unit (ODTU) signal is demultiplexed from the HO OPUk signal using the first clock. The ODTU signal is demapped to a lower order (LO) ODUj signal. The LO ODUj data is then smoothed using a smoothing function. Only one clock is used for the multiple stages of extraction of a LO ODUj from a HO OTUk signal.