Abstract: A current source providing a voltage-controlled variable-current reference is described which employs a conventional current mirror to supply a current to a diode-connected transistor, and to a plurality of controllable current paths, wherein the controllable current paths are controlled by voltages from a voltage sensing circuit so that predetermined amounts of current are drawn away from the diode-connected transistor as function of a controlled voltage, so that the diode-connected transistor generates a voltage as a function of the current flowing through it which voltage is used to control an output transistor and a current flowing through the output transistor.

Abstract: A power-up reset detector circuit is described which uses the threshold voltages of NMOS and PMOS transistors to detect the power-up of integrated circuits, and uses a current mirror to track power supply and process variations.

Abstract: A programmable logic array which can produce single level logic or can produce multiple level logic through the use of internal feedback loops. A plurality of input lines intersect a plurality of term lines and can be programmable coupled to the term lines. A number of term lines provide a feedback input which intersects all of the term lines and can be programmably coupled to the tem lines. Teh input lines and the feedback input lines form a single matrix with the term lines.

Abstract: An electrically erasable programmable memory device which is programmable in the manner of an EPROM and erasable in the manner of an EEPROM. A dielectric layer between the control gate and the floating gate is provided having a high dielectric constant. A thin, uniform gate dielectric layer is provided which demonstrates minimal trapping. Finally, an asymmetrical source/drain junction is provided wherein the source includes a shallow portion and a deeper portion, which deeper portion defines the overlap between the source and the floating gate. In the preferred embodiment the dielectric between the control gate and the floating gate comprises tantalum pentoxide, the thin dielectric layer comprises oxynitride, and the deep diffusion portion of the source comprises phosphorous.

Abstract: An improved field programmable matrix circuit. The matrix circuit includes a plurality of pairs of input lines having noninverted and inverted inputs. These input lines intersect a plurality of output column lines. A single transistor is used to provide a programmable connection to each column line from both the inverted and noninverted inputs of an input line pair. The transistor has a source, a drain and a gate with either the source or the drain coupled to a voltage potential and the other of the source or the drain coupled to an output column line. The gate is alternately coupled to a noninverted input, an inverted output, or a second voltage potential. The second voltage potential is coupled when it is desired to hold the transistor in an off state.

Abstract: In the present invention, asperity in the floating gate of an EPROM or EEPROM device is reduced. An improved process for fabricating ultrahigh coupling interpoly isolation dielectrics comprising a structure of oxide-nitride-oxide is disclosed. The first oxide is grown on undoped LPCVD polycrystalline silicon (polysilicon) to reduce the grain boundary-oxidation enhancement effect at the interface of floating gate polysilicon and interpoly oxide. This results in much higher breakdown capability of interpoly dielectrics. As a consequence, the shrinkage of the interpoly electrical thickness to an extent far beyond current limitation becomes possible. Implanted dopants through interpoly oxide into the floating gate polysilicon also eliminate the oxidation enhanced diffusion from conventional POCl.sub.3 doped polysilicon into tunnel oxide. The phosphorus induced trap in the tunnel oxide region are reduced. The EEPROM threshold window can remain open beyond 10.sup.6 cycles.

Abstract: An electrically erasable programmable memory device which is programmable in the manner of an EPROM and erasable in the manner of an EEPROM. A dielectric layer between the control gate and the floating gate is provided having a high dielectric constant. A thin, uniform gate dielectric layer is provided which demonstrates minimal trapping. Finally, an asymmetrical source/drain junction is provided wherein the source includes a shallow portion and a deeper portion, which deeper portion defines the overlap between the source and the floating gate. In the preferred embodiment the dielectric between the control gate and the floating gate comprises tantalum pentoxide, the thin dielectric layer comprises oxynitride, and the deep diffusion portion of the source comprises phosphorous.

Abstract: A method and apparatus for transferring a signal from a high voltage, low current source to a word select line in an electrically erasable, programmable read-only memory wherein a control signal is generated which is incremented in magnitude over time, the control signal being used to control a signal path between the high voltage, low current source and the desired word select line, such that the signal path is established whenever the difference between the control signal and the signal level on the word select line exceeds a predetermined threshold level, whereby the signal level on the desired word select line increases gradually over time to the high voltage level.