Abstract: An improved security circuit for a programmable logic array. One of the programmable elements of the array is designated as a security element, and its output is coupled to a latching mechanism. The output of the latching mechanism is coupled to a mechanism for disabling the read output of the array. The latching mechanism is enabled for a short time by a pulse when power is applied to the circuit. Thus, when power is first applied, the security fuse has not been set and the latch output will allow data to be read. While power is applied, all of the programmable elements can be set, including the security element. All the elements, including the security fuse, can then be verified by reading them out. When power is turned off and subsequently reapplied, the latch will then be enabled and the set security fuse level will appear at the latch output, thereby disabling the reading out of the program data.