Abstract: The present invention discloses a novel electronic package. This semiconductor packaging assembly is for supporting and containing an integrated circuit (IC) chip. The IC chip is supported on a single core double-layer substrate as a flip chip which is solder-bumped with low melting point solder, e.g., a 63 wt % Sn-37 wt % Pb eutectic solder. The flip chip is supported on a single core double-sided FR-4/5 or BT substrate provided with via holes to form via connections interconnecting the solder bumps to a land grid array disposed on the bottom surface of the substrate. The substrate is then surface mounted and soldered onto a printed circuit board which again is provided with low temperature 63 wt % Sn-37 wt % Pb eutectic solder paste for securely attaching the LGA CSP. Simplified processes are employed to assemble the electronic package with high yield processing steps, which can be conveniently carried out.

Abstract: The present invention discloses a new semiconductor ball grid array package for integrated circuits which have input and output counts higher than 250. The speed and performance characteristics of the semiconductor device contained in the package assembly are optimized while the packaging structure is simplified by utilizing only one dielectric layer and regular printed circuit board fabrication process. The complexities and higher cost for production of a multiple layer substrate for high-density interconnection configuration are thus resolved. The improved package assembly is achieved by implementing a segmented ring on one side of a substrate and a split plane on the other side thus forming a single layer substrate structure. The edges of the substrate are coated with metal layer to provide interlayer connections. The package assembly applies a cavity down configuration with an integrated heat spreader attached. The IC wire bonds within the cavity are sealed with an organic encapsulant.

Abstract: The present invention discloses a new substrate with two metal layer circuit structure and layout for semiconductor packaging. The speed and performance characteristics of the semiconductor device are optimized while the packaging structure is simplified by utilizing only one dielectric layer and conventional printed circuit board fabrication process. The difficulties encountered due to the complexities and higher cost of production required for the multiple layer and high density configuration are thus avoided. The improved circuit structure is achieved by implementing a segmented ring on one side of a substrate and a split plane on the other side thus forming a single layer substrate structure. The edges of the substrate are coated with metal layer to provide inter-layer connections.