Abstract: Embodiment of a storage stack are disclosed whereby increased performance and other technical improvements are achieved by an application requesting access (e.g., asynchronously) to an address, returning a buffer, and the application issuing a buffer release when the operation is complete.

Abstract: Systems and methods (including hardware and software) are disclosed for us in a multi-core, multi-socket server with many RDMA network adapters and NVME solid state drives. One of the features of the subject matter is to optimize the total IO throughput of the system by first replacing software locks with non-interruptible event handlers running on specific CPU cores that own individual software data structures and hardware queues, and second by moving work to that CPU affinity without stalling due to software lock overhead.

Abstract: Methods and System for use on a memory controller are disclosed which provides atomic compute operations of any size using an asynchronous, pipelined message passing interface between clients and the memory controller.

Abstract: The present subject disclosure provides a switch architecture with data and control path systolic array that can be used for real time data analysis or Artificial Intelligence (AI) learning. A systolic array is described which analyzes the TLPs received by an uplink port and processes the TLPs according to pre-programmed rules. Then the TLP is forwarded to a destination port. The reverse operation is described as well.

Abstract: The disclosure provides a very flexible mechanism for a storage controller to create RAID stripes and to re-create corrupted stripes when necessary using the erasure coding scheme. Typically, this is known as a RAID 6 implementation/feature. The erasure code calculations are generated using the Galois Multiplication hardware and the system controller can pass any polynomial into the hardware on a per stripe calculation basis. The polynomial value is passed to the hardware via an input descriptor field. The descriptor controls the entire computation process.

Abstract: The present technique presents a hardware mechanism by which high performance computational engines utilize external/system memory buffers for data source and sync thus requiring a minimized amount of local buffering and imposing almost no buffer or data size limitations.

Abstract: Systems and methods (including hardware and software) are disclosed where all common RAID storage levels are implemented for multi-queue hardware by isolating RAID stripes to a single central processing unit (CPU) core affinity. Fixed CPU affinity is used for any piece of data that may be modified. Instead of blocking CPUs that must access or modify a piece of data, the request is efficiently moved to the CPU that owns that data. In this manner the system is completely asynchronous, efficient, and scalable.

Abstract: Systems and methods (including hardware and software) are disclosed where all common RAID storage levels are implemented for multi-queue hardware by isolating RAID stripes to a single central processing unit (CPU) core affinity. Fixed CPU affinity is used for any piece of data that may be modified. Instead of blocking CPUs that must access or modify a piece of data, the request is efficiently moved to the CPU that owns that data. In this manner the system is completely asynchronous, efficient, and scalable.

Abstract: The present subject disclosure presents a hardware mechanism and usage model for using a compute element of a systolic array to handle messages from an RQ (Receive Queue) to SQ (Send Queue) without requiring a copy between queues and also minimizing the local processor's interaction with the send and receive queue hardware.

Abstract: The present subject disclosure provides a PCIe switch architecture with data and control path systolic array that can be used for real time data analysis or Artificial Intelligence (AI) learning. A systolic array is described which analyzes the TLPs received by an uplink port and processes the TLPs according to pre-programmed rules. Then the TLP is forwarded to a destination port. The reverse operation is described as well.