Abstract: Embodiment of a storage stack are disclosed whereby increased performance and other technical improvements are achieved by an application requesting access (e.g., asynchronously) to an address, returning a buffer, and the application issuing a buffer release when the operation is complete.
Type:
Grant
Filed:
March 6, 2019
Date of Patent:
November 10, 2020
Assignee:
EXTEN Technologies, Inc.
Inventors:
Michael Enz, Rukhsana Ansari, Ashwin Kamath
Abstract: The present technique presents a hardware mechanism by which high performance computational engines utilize external/system memory buffers for data source and sync thus requiring a minimized amount of local buffering and imposing almost no buffer or data size limitations.
Type:
Grant
Filed:
December 15, 2017
Date of Patent:
October 8, 2019
Assignee:
Exten Technologies, Inc.
Inventors:
Daniel B. Reents, Ashwin Kamath, Michael Enz
Abstract: Systems and methods (including hardware and software) are disclosed where all common RAID storage levels are implemented for multi-queue hardware by isolating RAID stripes to a single central processing unit (CPU) core affinity. Fixed CPU affinity is used for any piece of data that may be modified. Instead of blocking CPUs that must access or modify a piece of data, the request is efficiently moved to the CPU that owns that data. In this manner the system is completely asynchronous, efficient, and scalable.
Abstract: The present subject disclosure presents a hardware mechanism and usage model for using a compute element of a systolic array to handle messages from an RQ (Receive Queue) to SQ (Send Queue) without requiring a copy between queues and also minimizing the local processor's interaction with the send and receive queue hardware.
Type:
Grant
Filed:
December 15, 2017
Date of Patent:
August 20, 2019
Assignee:
Exten Technologies, Inc.
Inventors:
Daniel B. Reents, Ashwin Kamath, Todd Blackmon, Michael Enz
Abstract: Systems and methods (including hardware and software) are disclosed where all common RAID storage levels are implemented for multi-queue hardware by isolating RAID stripes to a single central processing unit (CPU) core affinity. Fixed CPU affinity is used for any piece of data that may be modified. Instead of blocking CPUs that must access or modify a piece of data, the request is efficiently moved to the CPU that owns that data. In this manner the system is completely asynchronous, efficient, and scalable.
Abstract: The present subject disclosure provides a PCIe switch architecture with data and control path systolic array that can be used for real time data analysis or Artificial Intelligence (AI) learning. A systolic array is described which analyzes the TLPs received by an uplink port and processes the TLPs according to pre-programmed rules. Then the TLP is forwarded to a destination port. The reverse operation is described as well.
Type:
Grant
Filed:
April 24, 2017
Date of Patent:
April 16, 2019
Assignee:
EXTEN Technologies, Inc.
Inventors:
Harish Kumar Shakamuri, Ashwin Kamath, Michael Enz